AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683172
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.4. JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9625 device's quick configuration register at address 0x05E. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9625 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Global setting for all configuration:

  • CS = 0
  • CF = 0
  • Subclass = 1
  • FPGA Management Clock (MHz) = 100
  • Character Replacement = Enabled
  • PCS Option = Hard PCS
Table 6.  Parameter Configuration
LMF HD S N N' ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 3 FPGA Link Clock (MHz) 4 FPGA Frame Clock (MHz) 4 Lane Rate (Gbps) DDC enabled Data Pattern
118 0 4 16 5 16 2500 625 156.25 78.125 6.25 Yes PRBS-23 Ramp
214 0 4 16 5 16 2500 625 156.25 156.25 6.25 Yes PRBS-23 Ramp
412 0 4 16 5 16 2500 625 156.25 156.25 6.25 Yes PRBS-23 Ramp
611 1 4 12 12 2500 625 156.25 156.25 6.25 No PRBS-23 Ramp
811 1 4 12 16 2500 625 156.25 156.25 6.25 No PRBS-23 Ramp
3 The device clock is used to clock the transceiver.
4 The frame clock and link clock are derived from the device clock using an internal PLL.
5 The 16-bit test pattern is an output from the JESD204 test pattern generator block in the AD9625.
Level Two Title