AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683172
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.2. Hardware Setup

An Intel® Stratix® 10 GX L-Tile FPGA Development Kit (ES Edition) is used with the ADI AD9625 daughter card module installed to the development board’s FMC connector.

  • The AD9625 EVM derives power from FMC pins.
  • An internal on-board oscillator present on the AD9625 EVM provides 2.5 GHz device clock to the ADC.
  • The AD9625 provides a divide by 4 version of this clock (625 MHz) to FPGA through FMC pins.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
  • The SYSREF is provided to the ADC through FMC pins.
Figure 1. Hardware Setup

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram

In this setup, where LMF = 811, the data rate of transceiver lanes is 6.25 Gbps. The oscillator on the EVM is used for clocking both the EVM and the FPGA. The oscillator generates a fixed clock of frequency 2500 MHz. This clock is used as sampling frequency by the ADC. A divide by 4 version of this clock (625 MHz) is made available to FPGA through FMC pins. FPGA uses this clock as the reference clock for transceiver and generate internal link and frame clocks. The ADC registers are programmed through 3-wire SPI interface. Although the maximum lane rate supported by the JESD converter is 6.5 Gbps, the fixed oscillator on the EVM restricts the lane rate to 6.25 Gbps. The converter operates in a single JESD link in all configurations with a maximum of 8 lanes.

Level Two Title