AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

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ID 683163
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Device Migration Overview 3. Hardware Design Guidelines 4. Intel® Quartus® Prime Software Design Migration 5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package
3. Hardware Design Guidelines x
3.1. Power Pin Migration Guidelines 3.2. I/O Pins Migration Guidelines 3.3. VREF Pin Migration Guidelines 3.4. RZQ Pin Migration Guidelines
4. Intel® Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for 1SG040HH2F3512VG-1SG065HH3F3512VG Devices 4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices
1. Introduction
2. Device Migration Overview
3. Hardware Design Guidelines
4. Intel® Quartus® Prime Software Design Migration
5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

3.1. Power Pin Migration Guidelines

The following table describes the power pin design guidelines for the design migration. The focused power pins are VCCIO I/O banks 3A, 3B, 3C, and 3D which require pre-design consideration.
Table 4.  Power Pin Board Design Guidelines
Pin I/O Bank Board Design Guidelines
Power Pin (VCCIO) 3A The bank 3A can support the equivalent VCCIO voltage level from the migration device. Therefore, the power rail connection can remain. You may power down the unused I/O banks by connecting their VCCIO pin to GND.
3B The bank 3B can support the equivalent VCCIO voltage level from the migration device. Therefore, the power rail connection can remain. You may power down the unused I/O banks by connecting their VCCIO pin to GND.
3C The supported VCCIO voltage level of the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 is 3.0V or 3.3V. It is not migratable to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device, as it supports only 1.2V, 1.5V, and 1.8V. The same conditions apply when migrating from the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device to the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device.

Your board design must have an option to connect the VCCIO to GND when the I/O bank is not in use after the migration or the power rail changes to the desired VCCIO voltage level after the migration. You must pre-design the power rail by changing the 0Ω resistor options for the voltage selection as shown in Figure 1.

3D The VCCIO3D for the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device supports only 1.8V. If the target migration device is also using the same voltage level, it is directly migratable. Otherwise, you must pre-design the power rails by changing the 0Ω resistor options for the voltage selection as shown in Figure 2.
Figure 1.  VCCIO Pin for Bank 3C
Figure 2.  VCCIO Pin for Bank 3D
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