AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

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ID 683163
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Device Migration Overview 3. Hardware Design Guidelines 4. Intel® Quartus® Prime Software Design Migration 5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package
3. Hardware Design Guidelines x
3.1. Power Pin Migration Guidelines 3.2. I/O Pins Migration Guidelines 3.3. VREF Pin Migration Guidelines 3.4. RZQ Pin Migration Guidelines
4. Intel® Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for 1SG040HH2F3512VG-1SG065HH3F3512VG Devices 4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices
1. Introduction
2. Device Migration Overview
3. Hardware Design Guidelines
4. Intel® Quartus® Prime Software Design Migration
5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices

The example design used in this migration is a basic design to address the assignment and the I/O standard issues. The following figure shows the snapshot of the design with pin assignments.

Figure 22. Example Design with Pin Assignments
  1. To start the migration between 1SX065HH3F3512LG-1SX040HH2F3512LG devices, right click on Device in the project navigator window. The Migration Devices window will pop up.
    Figure 23. Migration Devices
  2. After choosing the device for migration (1SX040HH2F3512LG), click OK and then you can check the assignment in the .qsf file. If you do not specify at least one migration device in the Migration Devices dialog box, the field displays 0 Migration Devices Selected.
    Figure 24. Set Global Assignment
  3. After specifying the device to migrate, follow the step mentioned earlier and make the non-migratable I/O as tri-stated and then compile the design.
    Figure 25. Error Message
  4. The compilation report shows errors related to the pin assignments location. Navigate to the Pin Planner and remove the location assignment of those pins to make them unused pins and they can be tri-stated.
    Figure 26. Pin Assignments
  5. After removing the assignments, compile the design. You might encounter more compile errors that are pointing you towards the non-compatibility I/O standard in bank 3A and 3D.
    Figure 27. Compilation Error
  6. After you have removed the assignments which show incompatibility as shown in Figure 28, compiling the design again will give a successful compilation.
    Note: You can remove the unused logic design and disconnect the pins from the Intel® Quartus® Prime software. If you do not remove these unusable pins from the Intel® Quartus® Prime design, the software will automatically fit a location for these pins with the design connected.
    Figure 28. Pin Assignments
    Figure 29. Design Compilation
  7. Alternatively, if you have the flexibility of changing the non-migratable pins and their I/O standard, you can check the Pin Migration View window to obtain the information about the suitability of the pins for the device migration. You can change the pins accordingly for a successful compilation.
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