AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

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ID 683163
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Device Migration Overview 3. Hardware Design Guidelines 4. Intel® Quartus® Prime Software Design Migration 5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package
3. Hardware Design Guidelines x
3.1. Power Pin Migration Guidelines 3.2. I/O Pins Migration Guidelines 3.3. VREF Pin Migration Guidelines 3.4. RZQ Pin Migration Guidelines
4. Intel® Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for 1SG040HH2F3512VG-1SG065HH3F3512VG Devices 4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices
1. Introduction
2. Device Migration Overview
3. Hardware Design Guidelines
4. Intel® Quartus® Prime Software Design Migration
5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

3. Hardware Design Guidelines

This section provides the hardware design guidelines with consideration of the device migration compatibilities covered in the previous section. As mentioned earlier, the I/O banks for 2K, 2L, 2M, 2N, and 3B are fully compatible for device migration.

Similarly, power pins such as VCC, VCCPT, and VCCA_PLL are fully compatible and migratable between these devices. For more information, refer to the guidelines listed in Intel® Stratix® 10 Device Family Pin Connection Guidelines.


Section Content
Power Pin Migration Guidelines
I/O Pins Migration Guidelines
VREF Pin Migration Guidelines
RZQ Pin Migration Guidelines

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