HDMI Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683156
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios® V Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Setting Up the Hardware 4.3.2. Generating the Design 4.3.3. Including HDCP Production Keys 4.3.4. Compiling the Design 4.3.5. Viewing the Results
4.3.3. Including HDCP Production Keys x
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. Viewing the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide

2.12. Hardware Setup

The HDMI FRL-enabled design example is HDMI 2.1 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the HDMI sink input. The design supports both HDMI 2.1 or HDMI 2.0/1.4b source and sink.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you want to use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Arria® 10 FPGA development kit and Bitec HDMI 2.1 daughter card. You may modify the settings for your own board.
On-board Push Button and User LED Functions
Push Button/LED Function
cpu_resetn Press once to perform system reset.
user_dipsw

User-defined DIP switch to toggle the passthrough mode.

  • OFF (default position) = Passthrough

    HDMI RX on the FPGA gets the EDID from external sink and presents it to the external source it is connected to.

  • ON = You may control the RX maximum FRL rate from the Nios® V terminal. The command modifies the RX EDID by manipulating the maximum FRL rate value.

Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates.

user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1] Reserved.
user_pb[2] Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
USER_LED[0] RX TMDS clock PLL lock status.
  • 0 = Unlocked
  • 1 = Locked
USER_LED[1] RX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
USER_LED[2] RX link speed clock PLL, and RX video and FRL clock PLL lock status.
  • 0 = Either one of the RX clock PLL is unlocked
  • 1 = Both RX clock PLLs are locked
USER_LED[3] RX HDMI core alignment and deskew lock status.
  • 0 = At least 1 channel is unlocked
  • 1 = All channels are locked
USER_LED[4] RX HDMI video lock status.
  • 0 = Unlocked
  • 1 = Locked
USER_LED[5] TX link speed clock PLL, and TX video and FRL clock PLL lock status.
  • 0 = Either one of the TX clock PLL is unlocked
  • 1 = Both TX clock PLLs are locked
USER_LED[6] TX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
USER_LED[7] TX link training status.
  • 0 = Failed
  • 1 = Passed
Level Two Title