HDMI Arria® 10 FPGA IP Design Example User Guide

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ID 683156
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios® V Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Setting Up the Hardware 4.3.2. Generating the Design 4.3.3. Including HDCP Production Keys 4.3.4. Compiling the Design 4.3.5. Viewing the Results
4.3.3. Including HDCP Production Keys x
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. Viewing the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Arria® 10 FPGA IP Design Example User Guide

3.6. Clocking Scheme

The clocking scheme illustrates the clock domains in the HDMI Intel® FPGA IP design example.
Figure 26.  HDMI Intel® FPGA IP Design Example Clocking Scheme ( Quartus® Prime Pro Edition)
Figure 27.  HDMI Intel® FPGA IP Design Example Clocking Scheme ( Quartus® Prime Standard Edition)
Table 39.  Clocking Scheme Signals
Clock Signal Name in Design Description
TX IOPLL/ TX PLL Reference Clock 1 hdmi_clk_in

Reference clock to the TX IOPLL and TX PLL. The clock frequency is the same as the expected TMDS clock frequency from the HDMI TX TMDS clock channel.

For this HDMI Intel® FPGA IP design example, this clock is connected to the RX TMDS clock for demonstration purpose. In your application, you need to supply a dedicated clock with TMDS clock frequency from a programmable oscillator for better jitter performance.

Note: Do not use a transceiver RX pin as a TX PLL reference clock. Your design fails to fit if you place the HDMI TX refclk on an RX pin.
TX Transceiver Clock Out tx_clk

Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

TX transceiver clock out frequency = Transceiver data rate/ (Symbol per clock*10)
TX PLL Serial Clock tx_bonding_clocks

Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.
TX/RX Link Speed Clock ls_clk

Link speed clock. The link speed clock frequency depends on the expected TMDS clock frequency, oversampling factor, symbols per clock, and TMDS bit clock ratio.

TMDS Bit Clock Ratio Link Speed Clock Frequency
0 TMDS clock frequency/ Symbol per clock
1 TMDS clock frequency *4 / Symbol per clock
TX/RX Video Clock vid_clk
Video data clock. The video data clock frequency is derived from the TX link speed clock based on the color depth.
TMDS Bit Clock Ratio Video Data Clock Frequency
0 TMDS clock/ Symbol per clock/ Color depth factor
1 TMDS clock *4 / Symbol per clock/ Color depth factor
Bits per Color Color Depth Factor
8 1
10 1.25
12 1.5
16 2.0
RX TMDS Clock tmds_clk_in

TMDS clock channel from the HDMI RX and connects to the reference clock to the IOPLL.

RX CDR Reference Clock 0 /TX PLL Reference Clock 0 fr_clk

Free running reference clock to RX CDR and TX PLL. This clock is required for power-up calibration.
RX CDR Reference Clock 1 iopll_outclk0

Reference clock to the RX CDR of RX transceiver.

Data Rate RX Reference Clock Frequency

Data rate <1 Gbps

5× TMDS clock frequency

1 Gbps< Data rate <3.4 Gbps

TMDS clock frequency

Data rate >3.4 Gbps

4× TMDS clock frequency
  • Data Rate <1 Gbps: For oversampling to meet transceiver minimum data rate requirement.
  • Data Rate >3.4 Gbps: To compensate for the TMDS bit rate to clock ratio of 1/40 to maintain the transceiver data rate to clock ratio at 1/10.
Note: Do not use a transceiver RX pin as a CDR reference clock. Your design fails to fit if you place the HDMI RX refclk on an RX pin.
RX Transceiver Clock Out rx_clk

Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

RX transceiver clock out frequency = Transceiver data rate/ (Symbol per clock*10)
Management Clock

mgmt_clk

A free running 100 MHz clock for these components:
  • Avalon-MM interfaces for reconfiguration
    • The frequency range requirement is between 100–125 MHz.
  • PHY reset controller for transceiver reset sequence
    • The frequency range requirement is between 1–500 MHz.
  • IOPLL Reconfiguration
    • The maximum clock frequency is 100 MHz.
  • RX Reconfiguration for management
  • CPU
  • I2C Master
I2C Clock i2c_clk

A 100 MHz clock input that clocks I2C slave, SCDC registers in the HDMI RX core, and EDID RAM.

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