in_ready |
ready |
Output |
Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the in_ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge. |
in_valid |
valid |
Input |
Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal. |
in_data[] |
data |
Input |
Data input for each codeword, symbol by symbol. Valid only when you assert the in_valid signal. For Qsys systems, the in_data bus is: [in_numn,in_numcheck,data] If you have no variable check it is: [numn,data] For example, for a maximum codeword length of 255 corresponding to 8 bits:
- in_data[7:0] = data
- in_data[15:0] = numn
|
in_channel |
channel |
Input |
Specifies the channel number for data the IP core transfers on the current cycle. The in_channel signal is available only when you configure the IP core to support multiple channels. |
in_startofpacket |
sop |
Input |
Start of packet (codeword) signal. |
in_endofpacket |
eop |
Input |
End of packet (codeword) signal. |
in_error |
error |
Input |
Error signal. Specifies if the input data symbol is an error and whether the decoder can consider it as an erasure. Erasures-supporting decoders only. |
out_startofpacket |
sop |
Output |
Start of packet (codeword) signal. This signal indicates the codeword boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the start of packet is present on the in_data[] bus. The IP core asserts this signal on the first transfer of every codeword. |
out_endofpacket |
eop |
Output |
End of packet (codeword) signal. This signal indicates the packet boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the end of packet is present on the in_data[] bus. The IP core asserts this signal on the last transfer of every packet. |
out_ready |
ready |
Input |
Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal. If the source is unable to provide new data, it deasserts out_valid for one or more clock cycles until it is prepared to drive valid data interface signals. |
out_valid |
valid |
Output |
Data valid signal. The IP core asserts the out_valid signal high, whenever a valid output is on out_data ; the IP core deasserts the signal when there is no valid output on out_data . |
out_data |
data |
Output |
Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered. |
out_channel |
channel |
Output |
Specifies the channel whose result is presented at out_data . Available only when you configure the IP core to support multiple channels. |
out_error |
error |
Output |
Indicates non-correctable codeword (decoder only). Valid when the IP core asserts out_endofpacket . |