Reed-Solomon II IP Core User Guide

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ID 683144
Date 11/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. About the Reed-Solomon II IP Core 2. Reed-Solomon II IP Core Getting Started 3. Reed-Solomon II IP Core Functional Description 4. Document Revision History
1. About the Reed-Solomon II IP Core x
1.1. Altera DSP IP Core Features 1.2. Reed-Solomon II IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Reed-Solomon II IP Core Release Information 1.6. Reed-Solomon II IP Core Performance and Resource Utilization
2. Reed-Solomon II IP Core Getting Started x
2.1. Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores 2.4. Simulating Altera IP Cores in other EDA Tools 2.5. DSP Builder Design Flow
2.1. Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores x
2.3.1. Files Generated for Altera IP Cores and Qsys Systems
3. Reed-Solomon II IP Core Functional Description x
3.1. Architecture 3.2. Reed-Solomon II IP Core Parameters 3.3. Reed-Solomon II IP Core Interfaces and Signals
3.1. Architecture x
3.1.1. Reed-Solomon II Encoder 3.1.2. Reed-Solomon II Decoder 3.1.3. Multiple Input Channels
3.3. Reed-Solomon II IP Core Interfaces and Signals x
3.3.1. Avalon-ST Interfaces in DSP IP Cores 3.3.2. Reed-Solomon II IP Core Signals
1. About the Reed-Solomon II IP Core
2. Reed-Solomon II IP Core Getting Started
3. Reed-Solomon II IP Core Functional Description
4. Document Revision History

3.1.3. Multiple Input Channels

The RS II IP core processes multiple input channels simultaneously.

The IP core receives codewords in a fixed pattern. Symbols coming in through the channels are interleaved. The IP core samples the first symbol of channel one on the first rising clock edge, then the first symbol of channel two on the second rising clock edge, etc. Both information and check symbols are output in the same sequence.

Figure 9. Codeword for C Channels and N SymbolsThe channel signal indicates the channel associated to the current symbol. The channel sequence is fixed. startofpacket indicates the first symbol of a codeword per channel. For a C-channel codeword, startofpacket must be high for C consecutive cycles. endofpacket indicates the last symbol of a codeword per channel. For a C-channel codeword, endofpacket must be high for C consecutive cycles.
Note: The startofpacket and endofpacket governs the number of symbols per codeword, N. The IP core does not verify if N exceeds the maximum symbols per codeword. The IP core also does not verify the channel or data pattern. You must ensure that the codeword sent to the IP core has a valid N and a valid pattern.
Figure 10. Encoder Timing—Two Channels For a two-channel codeword, the encoder asserts the in_startofpacket and in_endofpacket signals for two consecutive cycles.
Figure 11. Decoder Timing—Two ChannelsFor a two-channel codeword, the decoder asserts the in_startofpacket and in_endofpacket signals for two consecutive cycles.
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