Reed-Solomon II IP Core User Guide

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ID 683144
Date 11/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. About the Reed-Solomon II IP Core 2. Reed-Solomon II IP Core Getting Started 3. Reed-Solomon II IP Core Functional Description 4. Document Revision History
1. About the Reed-Solomon II IP Core x
1.1. Altera DSP IP Core Features 1.2. Reed-Solomon II IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Reed-Solomon II IP Core Release Information 1.6. Reed-Solomon II IP Core Performance and Resource Utilization
2. Reed-Solomon II IP Core Getting Started x
2.1. Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores 2.4. Simulating Altera IP Cores in other EDA Tools 2.5. DSP Builder Design Flow
2.1. Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores x
2.3.1. Files Generated for Altera IP Cores and Qsys Systems
3. Reed-Solomon II IP Core Functional Description x
3.1. Architecture 3.2. Reed-Solomon II IP Core Parameters 3.3. Reed-Solomon II IP Core Interfaces and Signals
3.1. Architecture x
3.1.1. Reed-Solomon II Encoder Shortened Codewords 3.1.2. Reed-Solomon II Decoder 3.1.3. Multiple Input Channels
3.3. Reed-Solomon II IP Core Interfaces and Signals x
3.3.1. Avalon-ST Interfaces in DSP IP Cores 3.3.2. Reed-Solomon II IP Core Signals
1. About the Reed-Solomon II IP Core
2. Reed-Solomon II IP Core Getting Started
3. Reed-Solomon II IP Core Functional Description
4. Document Revision History

3.1.1. Reed-Solomon II Encoder

When the encoder receives data symbols, it generates check symbols for a given codeword and sends the input codeword together with the check symbols to the output interface. The encoder uses backpressure on the upstream component when it generates the check symbols.
Figure 5. Reed-Solomon II Codeword Encoding
Figure 6. Encoder Timing—One ChannelShows the timing diagram of the RS II encoder with one channel.
The in_startofpacket signal starts a codeword; the in_endofpacket signals its termination. An asserted in_valid signal indicates valid data. The in_startofpacket signal is only valid when you assert the in_valid signal. For a 1-channel codeword, assert the in_startofpacket and in_endofpacket signals for one clock cycle. The encoder uses backpressure by deasserting the in_ready signal when it receives the in_endofpacket signal. During this time, the encoder signals that it cannot accept more incoming symbols and generates the check symbols for the current codeword. The IP core does not verify if the number of symbols (N) exceeds the maximum symbols per codeword. You must ensure that the codeword sent to the core has a valid N. The reset_reset_n signal is active low and you can assert this signal asynchronously. However, you have to deassert the reset_reset_n signal synchronously with the clk_clk signal.

Shortened Codewords

The RS II IP core supports shortened codewords. A shortened codeword contains fewer symbols than the maximum value of N, which is 2M –1, where N is the total number of symbols per codeword and M is the number of bits per symbol. A shortened codeword is mathematically equivalent to a maximum-length code with the extra data symbols at the start of the codeword set to 0. For example, (204,188) is a shortened codeword of (255,239). Both of these codewords use the same number of check symbols, 16. To use shortened codewords with the decoder, use the parameter editor to set the codeword length to the correct value; for the encoder assert endofpacket once it generates enough symbols.

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