Quartus® Prime Pro Edition User Guide: Design Constraints

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Quartus® Prime GUI 1.1.4. Specifying Timing Constraints
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify NoC Constraints in NoC Assignment Editor 1.1.2.3. Specify I/O Constraints in Pin Planner 1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.5. Adjust Constraints with the Chip Planner 1.1.2.6. Constraining Designs with the Design Partition Planner
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
1.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
1.1.2.2.1. NoC Assignment Editor Interface Controls 1.1.2.2.2. Troubleshooting NoC Assignment Editor
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner General Tool Flow 2.1.3. Interface Planner NoC Tool Flow 2.1.4. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner General Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.3. Interface Planner NoC Tool Flow x
2.1.3.1. Placing NoC Design Elements Using Interface Planner
2.1.3.1. Placing NoC Design Elements Using Interface Planner x
2.1.3.1.1. Recommended Placement Order for NoC Elements in Interface Planner 2.1.3.1.2. High-Speed Interconnect NoC Locations in Interface Planner
2.1.4. Interface Planner Reports x
2.1.4.1. Report Summary 2.1.4.2. Report Pins 2.1.4.3. Report HSSI Channels 2.1.4.4. Report Clocks 2.1.4.5. Report Periphery Locations 2.1.4.6. Report Cell Connectivity 2.1.4.7. Report Instance Assignments 2.1.4.8. Report NoC Performance
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Constraining Dynamic Reconfiguration IP 2.2.4. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks
2.2.3. Constraining Dynamic Reconfiguration IP x
2.2.3.1. Defining a Dynamic Reconfiguration Group 2.2.3.2. Assigning Dynamic Reconfiguration Group Placement
2.2.4. Tile Interface Planner GUI Reference x
2.2.4.1. Flow Controls 2.2.4.2. Home Tab 2.2.4.3. Assignments Tab Controls 2.2.4.4. Plan Tab Controls 2.2.4.5. Tcl Console Window
2.2.4.4. Plan Tab Controls x
2.2.4.4.1. Design Tree and Filters 2.2.4.4.2. Reconfiguration Groups View 2.2.4.4.3. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel FPGA Device and I/O Terminology
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
3.2.6. Assigning Differential Pins x
3.2.6.1. Overriding I/O Placement Rules on Differential Pins
3.2.8. Entering Pin Assignments in HDL Code x
3.2.8.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
Answers to Top FAQs
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Quartus® Prime Pro Edition User Guides

2.2.1. Tile Interface Planner Terminology

Tile Interface Planner refers to the following terminology:
Table 22.  Tile Interface Planner Terminology
Term Description
Dynamic Reconfiguration Intel FPGA IP technology that allows you to modify some features of a supported multi-rate Intel® FPGA IP interface in real time while the FPGA remains in operation. For example, you can dynamically reconfigure the settings in the F-tile CPRI PHY Multi-Rate Intel® FPGA IP to run your design at different data rates and features for different IP "profiles."
Floorplan The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping the logical design hierarchy to physical regions in the device. Tile Interface Planner is a tile IP floorplanning tool.
IP building block

Intel® FPGA IP cores are comprised of building blocks that combine to provide all functionality of the IP. The Design Tree view in Tile Interface Planner displays each IP's building blocks. Building blocks can be movable, fixed, or always movable types.

  • Movable building blocks—building blocks are initially movable. Movable building blocks can be re-placed by the legality engine in potentially one of several legal locations to accommodate other building blocks. You can convert a movable building block to fixed by specifying a fixed placement location. The legality engine cannot change the placement of fixed building blocks. Movable building block placements appear in italic text in the Design Tree view. Movable building blocks have a dithered fill in Chip View.
  • Fixed building blocks—building blocks that you place in a fixed, legal location that the legality engine cannot change. You can convert a movable building block to fixed, and a fixed building block to movable. Fixed building block placements appear in plain text in the Design Tree view. Fixed building blocks have a solid fill In the Chip View.
  • Always movable building blocks—building blocks that are always movable by the legality engine and cannot be fixed. These building blocks must remain movable to prevent inadvertent conflicting constraints. Always movable building blocks appear in gray italic text in the Design Tree view.
Quartus® Prime Settings File (.qsf) Quartus® Prime software file that preserves project settings and assignments, including the placement of fixed IP building blocks and fixed tile assignments that you specify in Tile Interface Planner.
JSON file Quartus® Prime software internal file that preserves the most recent placement from the Logic Generation stage of the Compiler. You can load this placement when you click Update Assignments if you want the starting point for planning to include the last Logic Generation assignments.
Legal location Tile Interface Planner legality engine identifies the legal locations in the tile floorplan for placement of the IP or building block that you select in the Design Tree.
Legality engine Tile Interface Planner function that generates valid legal locations for tile placement, and places movable and always movable building blocks in the tile plan.
Placed design element IP or building block that you or the legality engine has assigned to a fixed or movable legal location.

Support-Logic Generation stage

A Compiler stage, preceding Analysis & Synthesis, that includes the Design Analysis and Logic Generation sub-stages. This stage is only present when targeting F-tile.
  • Design Analysis stage—A Compiler stage, preceding Analysis & Synthesis, that elaborates the design RTL to extract design information about component IP targeting F-tile. You must run this stage before running Tile Interface Planner. This stage is not present for other FPGA device families or for designs without required IP.
  • Logic Generation stage—A Compiler stage, following Design Analysis, that uses your Tile Interface Plan to generate logic for synthesis and implementation of your tile configuration plan. You must run Logic Generation after Design Analysis before you can synthesize your tile plan.
Tile plan One or more fixed placements that you define and save in Tile Interface Planner using the (.qsf).
Unplaced design element IP or building blocks that are unassigned to a fixed or movable legal location.
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