Quartus® Prime Pro Edition User Guide: Design Constraints

Download PDF
ID 683143
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Quartus® Prime GUI 1.1.4. Specifying Timing Constraints
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify NoC Constraints in NoC Assignment Editor 1.1.2.3. Specify I/O Constraints in Pin Planner 1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.5. Adjust Constraints with the Chip Planner 1.1.2.6. Constraining Designs with the Design Partition Planner
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
1.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
1.1.2.2.1. NoC Assignment Editor Interface Controls 1.1.2.2.2. Troubleshooting NoC Assignment Editor
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner General Tool Flow 2.1.3. Interface Planner NoC Tool Flow 2.1.4. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner General Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.3. Interface Planner NoC Tool Flow x
2.1.3.1. Placing NoC Design Elements Using Interface Planner
2.1.3.1. Placing NoC Design Elements Using Interface Planner x
2.1.3.1.1. Recommended Placement Order for NoC Elements in Interface Planner 2.1.3.1.2. High-Speed Interconnect NoC Locations in Interface Planner
2.1.4. Interface Planner Reports x
2.1.4.1. Report Summary 2.1.4.2. Report Pins 2.1.4.3. Report HSSI Channels 2.1.4.4. Report Clocks 2.1.4.5. Report Periphery Locations 2.1.4.6. Report Cell Connectivity 2.1.4.7. Report Instance Assignments 2.1.4.8. Report NoC Performance
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Constraining Dynamic Reconfiguration IP 2.2.4. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks
2.2.3. Constraining Dynamic Reconfiguration IP x
2.2.3.1. Defining a Dynamic Reconfiguration Group 2.2.3.2. Assigning Dynamic Reconfiguration Group Placement
2.2.4. Tile Interface Planner GUI Reference x
2.2.4.1. Flow Controls 2.2.4.2. Home Tab 2.2.4.3. Assignments Tab Controls 2.2.4.4. Plan Tab Controls 2.2.4.5. Tcl Console Window
2.2.4.4. Plan Tab Controls x
2.2.4.4.1. Design Tree and Filters 2.2.4.4.2. Reconfiguration Groups View 2.2.4.4.3. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel FPGA Device and I/O Terminology
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
3.2.6. Assigning Differential Pins x
3.2.6.1. Overriding I/O Placement Rules on Differential Pins
3.2.8. Entering Pin Assignments in HDL Code x
3.2.8.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
Answers to Top FAQs
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Quartus® Prime Pro Edition User Guides

2.1.3.1.2. High-Speed Interconnect NoC Locations in Interface Planner

When placing NoC initiators and targets, refer to the following tables to correlate locations with NoC elements visible in the Interface Planner.

Table 12.  Top-Edge High-Speed Interconnect NoC Locations in Interface Planner
NoC Segment Initiator Target Interface Planner Location
PLL/SSM NOCPLL_X11_Y417_N221 NOCSSM_X11_Y417_N220
GPIO-B_0 I0 T0 NOCINITIATOR_X27_Y417_N202 NOCTARGET_X27_Y417_N200
I1 AXI4 Lite NOCINITIATOR_X42_Y417_N202 NOCAXILITETARGET_X42_Y417_N200
I2 T2 NOCINITIATOR_X53_Y417_N202 NOCTARGET_X53_Y417_N200
GPIO-B_1 I0 T0 NOCINITIATOR_X79_Y417_N202 NOCTARGET_X79_Y417_N200
I1 AXI4 Lite NOCINITIATOR_X94_Y417_N202 NOCAXILITETARGET_X94_Y417_N200
I2 T2 NOCINITIATOR_X105_Y417_N202 NOCTARGET_X105_Y417_N200
UIB_L AXI4 Lite NOCAXILITETARGET_X123_Y417_N200
AXI4 Lite NOCAXILITETARGET_X129_Y417_N200
I0 AXI4 Lite NOCINITIATOR_X134_Y417_N202 NOCAXILITETARGET_X134_Y417_N200
T3 NOCTARGET_X140_Y417_N200
I1 T4 NOCINITIATOR_X150_Y417_N202 NOCTARGET_X150_Y417_N200
T5 NOCTARGET_X156_Y417_N200
I2 T6 NOCINITIATOR_X161_Y417_N202 NOCTARGET_X161_Y417_N200
T7 NOCTARGET_X167_Y417_N200
UIB_M T0 NOCTARGET_X177_Y417_N200
T1 NOCTARGET_X183_Y417_N200
I0 T2 NOCINITIATOR_X188_Y417_N202 NOCTARGET_X188_Y417_N200
I1 NOCINITIATOR_X204_Y417_N202
T3 NOCTARGET_X210_Y417_N200
I2 T4 NOCINITIATOR_X215_Y417_N202 NOCTARGET_X215_Y417_N200
T5 NOCTARGET_X221_Y417_N200
UIB_R T0 NOCTARGET_X231_Y417_N200
T1 NOCTARGET_X237_Y417_N200
I0 T2 NOCINITIATOR_X242_Y417_N202 NOCTARGET_X242_Y417_N200
T3 NOCTARGET_X248_Y417_N200
I1 T4 NOCINITIATOR_X258_Y417_N202 NOCTARGET_X258_Y417_N200
AXI4 Lite NOCAXILITETARGET_X264_Y417_N200
I2 AXI4 Lite NOCINITIATOR_X269_Y417_N202 NOCAXILITETARGET_X269_Y417_N200
AXI4 Lite NOCAXILITETARGET_X275_Y417_N200
GPIO-B_3 I0 T0 NOCINITIATOR_X296_Y417_N202 NOCTARGET_X296_Y417_N200
I1 AXI4 Lite NOCINITIATOR_X311_Y417_N202 NOCAXILITETARGET_X311_Y417_N200
I2 T2 NOCINITIATOR_X322_Y417_N202 NOCTARGET_X322_Y417_N200
GPIO-B/HPS T0 NOCTARGET_X346_Y417_N200
I0(fabric) AXI4 Lite NOCINITIATOR_X357_Y417_N204 NOCAXILITETARGET_X357_Y417_N200
I1(fabric) T2 NOCINITIATOR_X365_Y417_N204 NOCTARGET_X365_Y417_N200
I0(MPFE) AXI4 Lite I2(MPFE) NOCINITIATOR_X373_Y417_N202 NOCAXILITEINITIATOR_X373_Y417_N201 NOCINITIATOR_X373_Y417_N200
Table 13.  Bottom-Edge High-Speed Interconnect NoC Locations in Interface Planner
NoC Segment Initiator Target Interface Planner Location
PLL/SSM NOCPLL_X11_Y6_N221 NOCSSM_X11_Y6_N220
SDM I0 NOCINITIATOR_X28_Y6_N200
GPIO-B_1 I0 T0 NOCINITIATOR_X79_Y6_N202 NOCTARGET_X79_Y6_N200
I1 AXI4 Lite NOCINITIATOR_X94_Y6_N202 NOCAXILITETARGET_X94_Y6_N200
I2 T2 NOCINITIATOR_X105_Y6_N202 NOCTARGET_X105_Y6_N200
GPIO-B_2 I0 T0 NOCINITIATOR_X134_Y6_N202 NOCTARGET_X134_Y6_N200
I1 AXI4 Lite NOCINITIATOR_X149_Y6_N202 NOCAXILITETARGET_X149_Y6_N200
I2 T2 NOCINITIATOR_X160_Y6_N202 NOCTARGET_X160_Y6_N200
UIB_L AXI4 Lite NOCAXILITETARGET_X177_Y6_N200
AXI4 Lite NOCAXILITETARGET_X183_Y6_N200
I0 AXI4 Lite NOCINITIATOR_X188_Y6_N202 NOCAXILITETARGET_X188_Y6_N200
T3 NOCTARGET_X194_Y6_N200
I1 T4 NOCINITIATOR_X204_Y6_N202 NOCTARGET_X204_Y6_N200
T5 NOCTARGET_X210_Y6_N200
I2 T6 NOCINITIATOR_X215_Y6_N202 NOCTARGET_X215_Y6_N200
T7 NOCTARGET_X221_Y6_N200
UIB_M T0 NOCTARGET_X231_Y6_N200
T1 NOCTARGET_X237_Y6_N200
I0 T2 NOCINITIATOR_X242_Y6_N202 NOCTARGET_X242_Y6_N200
I1 NOCINITIATOR_X258_Y6_N202
T3 NOCTARGET_X264_Y6_N200
I2 T4 NOCINITIATOR_X269_Y6_N202 NOCTARGET_X269_Y6_N200
T5 NOCTARGET_X275_Y6_N200
UIB_R T0 NOCTARGET_X285_Y6_N200
T1 NOCTARGET_X291_Y6_N200
I0 T2 NOCINITIATOR_X296_Y6_N202 NOCTARGET_X296_Y6_N200
T3 NOCTARGET_X302_Y6_N200
I1 T4 NOCINITIATOR_X312_Y6_N202 NOCTARGET_X312_Y6_N200
AXI4 Lite NOCAXILITETARGET_X318_Y6_N200
I2 AXI4 Lite NOCINITIATOR_X323_Y6_N202 NOCAXILITETARGET_X323_Y6_N200
AXI4 Lite NOCAXILITETARGET_X329_Y6_N200
GPIO-B_3 I0 T0 NOCINITIATOR_X350_Y6_N202 NOCTARGET_X350_Y6_N200
I1 AXI4 Lite NOCINITIATOR_X365_Y6_N202 NOCAXILITETARGET_X365_Y6_N200
I2 T2 NOCINITIATOR_X376_Y6_N202 NOCTARGET_X376_Y6_N200
GPIO-B_4 I0 T0 NOCINITIATOR_X404_Y6_N202 NOCTARGET_X404_Y6_N200
I1 AXI4 Lite NOCINITIATOR_X419_Y6_N202 NOCAXILITETARGET_X419_Y6_N200
I2 T2 NOCINITIATOR_X430_Y6_N202 NOCTARGET_X430_Y6_N200
Level Two Title