F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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Date 10/22/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Introduction 3. IP Architecture and Functional Description 4. Advanced Features 5. Interfaces 6. Parameters 7. Testbench 8. Troubleshooting/Debugging 9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives 10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Implementation of Address Translation Services (ATS) in Endpoint Mode C. Packets Forwarded to the User Application in TLP Bypass Mode D. Root Port Enumeration
2. Introduction x
2.1. Overview 2.2. Features 2.3. Release Information 2.4. Device Family Support 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. IP Architecture and Functional Description x
3.1. Architecture 3.2. Functional Description 3.3. Avalon-ST TX/RX 3.4. Interrupts 3.5. Completion Timeout 3.6. Hot Plug 3.7. Power Management 3.8. Configuration Output Interface (COI) 3.9. Configuration Intercept Interface (EP Only) 3.10. Hard IP Reconfiguration Interface 3.11. PHY Reconfiguration Interface 3.12. Page Request Service (PRS) (EP Only)
3.1. Architecture x
3.1.1. Clocks 3.1.2. Refclk 3.1.3. Reset
3.2. Functional Description x
3.2.1. PMA/PCS 3.2.2. Data Link Layer 3.2.3. Transaction Layer
3.3. Avalon-ST TX/RX x
3.3.1. TLP Header and Data Alignment 3.3.2. Avalon-ST RX 3.3.3. Avalon-ST TX 3.3.4. Tag Allocation 3.3.5. Completion Buffer Size
3.3.2. Avalon-ST RX x
3.3.2.1. RX Flow Control
3.3.3. Avalon-ST TX x
3.3.3.1. TX Flow Control
3.4. Interrupts x
3.4.1. Legacy Interrupts 3.4.2. MSI 3.4.3. MSI-X
3.10. Hard IP Reconfiguration Interface x
3.10.1. Configuration Registers Access
3.10.1. Configuration Registers Access x
3.10.1.1. Direct User Avalon-MM Interface (Byte Access) 3.10.1.2. Debug Register Interface Access (Dword Access)
4. Advanced Features x
4.1. Virtualization Support 4.2. TLP Bypass Mode 4.3. Precision Time Measurement (PTM) 4.4. Scalable IOV
4.1. Virtualization Support x
4.1.1. Single Root I/O Virtualization (SR-IOV) 4.1.2. VirtIO
4.1.1. Single Root I/O Virtualization (SR-IOV) x
4.1.1.1. SR-IOV Implementation
4.1.1.1. SR-IOV Implementation x
4.1.1.1.1. Functional Level Reset (FLR)
4.1.2. VirtIO x
4.1.2.1. VirtIO Implementation 4.1.2.2. VirtIO Registers
5. Interfaces x
5.1. Overview 5.2. Clocks and Resets 5.3. Serial Data Interface 5.4. Avalon-ST Interface 5.5. Interrupt Interface 5.6. Hard IP Status Interface 5.7. Error Interface 5.8. 10-bit Tag Support Interface 5.9. Completion Timeout Interface 5.10. Power Management Interface 5.11. Hot Plug Interface (RP Only) 5.12. Configuration Output Interface 5.13. Configuration Intercept Interface (EP Only) 5.14. Hard IP Reconfiguration Interface 5.15. PHY Reconfiguration Interface 5.16. Page Request Service (PRS) Interface (EP Only) 5.17. FLR Interface Signals 5.18. PTM Interface Signals 5.19. VF Error Flag Interface Signals 5.20. VirtIO PCI Configuration Access Interface Signals
5.4. Avalon-ST Interface x
5.4.1. Avalon-ST RX Interface Signals 5.4.2. Avalon-ST TX Interface Signals
5.5. Interrupt Interface x
5.5.1. Legacy Interrupt Interface Signals 5.5.2. MSI Pending Bits Interface Signals
6. Parameters x
6.1. Top-Level Settings 6.2. Core Parameters
6.2. Core Parameters x
6.2.1. Avalon Parameters 6.2.2. Base Address Registers 6.2.3. PCI Express and PCI Capabilities Parameters 6.2.4. Device Identification Registers 6.2.5. Configuration, Debug and Extension Options
6.2.3. PCI Express and PCI Capabilities Parameters x
6.2.3.1. Device Capabilities 6.2.3.2. Link Capabilities 6.2.3.3. Legacy Interrupt Pin Register 6.2.3.4. MSI Capabilities 6.2.3.5. MSI-X Capabilities 6.2.3.6. Slot Capabilities 6.2.3.7. Latency Tolerance Reporting (LTR) 6.2.3.8. Process Address Space ID (PASID) 6.2.3.9. Device Serial Number Capability 6.2.3.10. Page Request Service (PRS) 6.2.3.11. Access Control Service (ACS) Capabilities 6.2.3.12. Power Management 6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers 6.2.3.14. Precision Time Measurement (PTM) 6.2.3.15. Address Translation Services (ATS) 6.2.3.16. TLP Processing Hints (TPH) 6.2.3.17. VirtIO Parameters
7. Testbench x
7.1. Endpoint Testbench 7.2. Test Driver Module 7.3. Root Port BFM 7.4. BFM Procedures and Functions
7.3. Root Port BFM x
7.3.1. BFM Memory Map 7.3.2. Configuration Space Bus and Device Numbering 7.3.3. Configuration of Root Port and Endpoint 7.3.4. Issuing Read and Write Transactions to the Application Layer
7.4. BFM Procedures and Functions x
7.4.1. ebfm_barwr Procedure 7.4.2. ebfm_barwr_imm Procedure 7.4.3. ebfm_barrd_wait Procedure 7.4.4. ebfm_barrd_nowt Procedure 7.4.5. ebfm_cfgwr_imm_wait Procedure 7.4.6. ebfm_cfgwr_imm_nowt Procedure 7.4.7. ebfm_cfgrd_wait Procedure 7.4.8. ebfm_cfgrd_nowt Procedure 7.4.9. BFM Configuration Procedures 7.4.10. BFM Shared Memory Access Procedures 7.4.11. BFM Log and Message Procedures 7.4.12. Verilog HDL Formatting Functions
7.4.9. BFM Configuration Procedures x
7.4.9.1. ebfm_cfg_rp_ep Procedure 7.4.9.2. ebfm_cfg_decode_bar Procedure
7.4.10. BFM Shared Memory Access Procedures x
7.4.10.1. Shared Memory Constants 7.4.10.2. shmem_write Task 7.4.10.3. shmem_read Function 7.4.10.4. shmem_display Verilog HDL Function 7.4.10.5. shmem_fill Procedure 7.4.10.6. shmem_chk_ok Function
7.4.11. BFM Log and Message Procedures x
7.4.11.1. ebfm_display Verilog HDL Function 7.4.11.2. ebfm_log_stop_sim Verilog HDL Function 7.4.11.3. ebfm_log_set_suppressed_msg_mask Task 7.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 7.4.11.5. ebfm_log_open Verilog HDL Function 7.4.11.6. ebfm_log_close Verilog HDL Function
7.4.12. Verilog HDL Formatting Functions x
7.4.12.1. himage1 7.4.12.2. himage2 7.4.12.3. himage4 7.4.12.4. himage8 7.4.12.5. himage16 7.4.12.6. dimage1 7.4.12.7. dimage2 7.4.12.8. dimage3 7.4.12.9. dimage4 7.4.12.10. dimage5 7.4.12.11. dimage6 7.4.12.12. dimage7
8. Troubleshooting/Debugging x
8.1. Hardware
8.1. Hardware x
8.1.1. Debugging Link Training Issues 8.1.2. Debugging Data Transfer and Performance Issues
8.1.1. Debugging Link Training Issues x
8.1.1.1. Generic Tools and Utilities 8.1.1.2. SignalTapII Logic Analyzer 8.1.1.3. Additional Debug Tools
8.1.1.3. Additional Debug Tools x
8.1.1.3.1. Using the Hard IP Reconfiguration Interface 8.1.1.3.2. Enable and Read LCRC and ECRC Error Count
8.1.2. Debugging Data Transfer and Performance Issues x
8.1.2.1. Advanced Error Reporting (AER) 8.1.2.2. Second-Level Debug Tools
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
B. Implementation of Address Translation Services (ATS) in Endpoint Mode x
B.1. Sending Translated/Untranslated Requests B.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) B.3. Invalidating Requests/Completions
C. Packets Forwarded to the User Application in TLP Bypass Mode x
C.1. EP TLP Bypass Mode (Upstream) C.2. RC TLP Bypass Mode (Downstream)
1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration

3.8. Configuration Output Interface (COI)

The Transaction Layer configuration output (tl_cfg) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems. The table below provides the tl_cfg_add_o[4:0] to tl_cfg_ctl_o[15:0] mapping.

Table 20.  Multiplexed Configuration Information available on tl_cfg_ctl
tl_cfg_add_o[4:0] tl_cfg_ctl_o[15:8] tl_cfg_ctl_o[7:0]
5'h00

[15]: memory space enable

[14]: IDO completion enable

[13]: perr_en

[12]: serr_en

[11]: fatal_err_rpt_en

[10]: nonfatal_err_rpt_en

[9]: corr_err_rpt_en

[8]: unsupported_req_rpt_en

Device control:

[7]: bus master enable

[6]: extended tag enable

[5:3]: maximum read request size

[2:0]: maximum payload size
5'h01

[15]: IDO request enable

[14]: No Snoop enable

[13]: Relaxed Ordering enable

[12:8]: Device number

 bus number
5'h02

[15]: pm_no_soft_rst

[14]: RCB control

[13]: Interrupt Request (IRQ) disable

[12:8]: PCIe Capability IRQ message number

[7:5]: reserved

[4]: system power control

[3:2]: system attention indicator control

[1:0]: system power indicator control
5'h03 Number of VFs [15:0]  
5'h04

[15]: reserved

[14]: AtomicOP Egress Block field (cfg_atomic_egress_block)

[13:9]: ATS Smallest Translation Unit (STU)[4:0]

[8]: ATS cache enable

[7]: ARI forward enable

[6]: Atomic request enable

[5:3]: TPH ST mode

[2:1]: TPH enable

[0]: VF enable
5'h05

[15:12]: auto negotiation link speed. Link speed encoding values are:

  • Gen1 : 0x1
  • Gen2 : 0x2
  • Gen3 : 0x4
  • Gen4 : 0x8

[11:1]: Index of Start VF [10:0]

[0]: reserved

  
5'h06 MSI Address [15:0]  
5'h07 MSI Address [31:16]  
5'h08 MSI Address [47:32]  
5'h09 MSI Address [63:48  
5'h0A MSI Mask [15:0]  
5'h0B MSI Mask [31:16]  
5'h0C

[15]: cfg_send_f_err

[14]: cfg_send_nf_err

[13]: cfg_send_cor_err

[12:8]: AER IRQ message number

[7]: Enable extended message data for MSI (cfg_msi_ext_data_en)

[6]: MSI-X func mask

[5]: MSI-X enable

[4:2]: Multiple MSI enable

[1]: 64-bit MSI

[0]: MSI enable
5'h0D MSI Data [15:0]  
5'h0E AER uncorrectable error mask [15:0]  
5'h0F AER uncorrectable error mask [31:16]  
5'h10 AER correctable error mask [15:0]  
5'h11 AER correctable error mask [31:16]  
5'h12 AER uncorrectable error severity [15:0]  
5'h13 AER uncorrectable error severity [31:16]  
5'h14 [15:8]: ACS Egress Control Register (cfg_acs_egress_ctrl_vec)

[7]: ACS function group enable (cfg_acs_func_grp_en)

[6]: ACS direct translated P2P enable (cfg_acs_p2p_direct_tranl_en)

[5]: ACS P2P egress control enable (cfg_acs_egress_ctrl_en)

[4]: ACS upstream forwarding enable (cfg_acs_up_forward_en)

[3]: ACS P2P completion redirect enable (cfg_acs_p2p_compl_redirect_en)

[2]: ACS P2P request redirect enable (cfg_acs_p2p_req_redirect_en)

[1]: ACS translation blocking enable (cfg_acs_at_blocking_en)

[0]: ACS source validation enable (RP) (cfg_acs_validation_en)

5'h15

[15:13]: reserved

[12]: PRS_RESP_FAILURE (cfg_prs_response_failure)

[11]: PRS_UPRGI (cfg_prs_uprgi)

[10]: PRS_STOPPED (cfg_prs_stopped)

[9]: PRS_RESET (cfg_prs_reset)

[8]: PRS_ENABLE (cfg_prs_enable)

[7:3]: reserved

[2:0]: ARI function group (cfg_ari_func_grp)
5'h16

PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [15:0]

 
5'h17

PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [31:16]

 
5'h18

[15:10]: reserved

[9]: Disable autonomous generation of LTR clear message (cfg_disable_ltr_clr_msg)

[8]: LTR mechanism enable (cfg_ltr_m_en)

[7]: Infinite credits for Posted header

[6]: Infinite credits for Posted data

[5]: Infinite credits for Completion header

[4]: Infinite credits for Completion data

[3]: End-end TLP prefix blocking (cfg_end2end_tlp_pfx_blck)

[2]: PASID enable (cfg_pf_pasid_en)

[1]: Execute permission enable (cfg_pf_passid_execute_perm_en)

[0]: Privileged mode enable (cfg_pf_passid_priv_mode_en)
5'h19

[15:9]: reserved

[8]: Slot control attention button pressed enable (cfg_atten_button_pressed_en)

[7]: Slot control power fault detect enable (cfg_pwr_fault_det_en)

[6]: Slot control MRL sensor changed enable (cfg_mrl_sensor_chged_en)

[5]: Slot control presence detect changed enable (cfg_pre_det_chged_en)

[4]: Slot control hot plug interrupt enable (cfg_hp_int_en)

[3]: Slot control command completed interrupt enable (cfg_cmd_cpled_int_en)

[2]: Slot control DLL state change enable (cfg_dll_state_change_en)

[1]: Slot control accessed (cfg_hp_slot_ctrl_access)

[0]: PF’s SERR# enable (cfg_br_ctrl_serren)
5'h1A LTR maximum snoop latency register (cfg_ltr_max_latency[15:0])  
5'h1B LTR maximum no-snoop latency register (cfg_ltr_max_latency[31:16])  
5'h1C [15:8]: enabled Traffic Classes (TCs) (cfg_tc_enable[7:0])

[5:0]: auto negotiation link width

6’h01 = x1

6’h02 = x2

6’h04 = x4

6’h08 = x8

6’h10 = x16
5'h1D MSI Data[31:16]  
5'h1E N/A  
5'h1F N/A  
The information on the Configuration Output (tl_cfg) bus is time-division multiplexed (TDM).
    • When tl_cfg_func[2:0] = 3'b000, tl_cfg_ctl[31:0] drive out the PF0 Configuration Space register values.
    • Then, tl_cfg_func[2:0] are incremented to 3'b001.
    • When tl_cfg_func[2:0] = 3'b001, tl_cfg_ctl[31:0] drive out the PF1 Configuration Space register values.
    • This pattern repeats to cover all enabled PFs.
Figure 36. Configuration Output Interface Timing Diagram
Note: This timing diagram is applicable for all topologies except 1x4.
Figure 37. Configuration Output Interface Timing Diagram [For 1 x4 Configuration or Topology H]
Note: In 1 x4 Configuration or Topology H, one data consumes 5 clock cycles.
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