AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide

Download PDF
ID 683139
Date 4/06/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Implementation Overview 3. Implementation Consideration 4. Evaluation Results 5. Conclusion 6. Document Revision History for AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide
3. Implementation Consideration x
3.1. Ideality Factor (η-Factor) Mismatch 3.2. Series Resistance Error 3.3. Temperature Diode Beta Variation 3.4. Differential Input Capacitor 3.5. Offset Compensation
4. Evaluation Results x
4.1. Evaluation with Maxim Integrated* 's MAX31730 Temperature Sensing Chip Evaluation Board 4.2. Evaluation with Texas Instruments* 's TMP468 Temperature Sensing Chip Evaluation Board
1. Introduction
2. Implementation Overview
3. Implementation Consideration
4. Evaluation Results
5. Conclusion
6. Document Revision History for AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide

4.1. Evaluation with Maxim Integrated* 's MAX31730 Temperature Sensing Chip Evaluation Board

This evaluation was conducted with setup steps as described in Offset Compensation .

The data was collected before and after applying the offset compensation. Different offset temperature was applied to different Intel® FPGA blocks because a single offset value cannot be applied on all blocks. The following figures show the results.

Figure 8. Data for Intel® Stratix® 10 Core Fabric


Figure 9. Data for Intel® FPGA H-Tile and L-Tile


Figure 10. Data for Intel® FPGA E-Tile


Figure 11. Data for Intel® FPGA P-Tile


Level Two Title