AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

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ID 683135
Date 2/09/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12J4000 EVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 733 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

1.4.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output long transport layer test pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The long transport layer test pattern (as defined in the JESD204B specification section 5.1.6.3) is observed at the data output of the RX transport layer.

The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3.  Long Transport Layer Test Cases

Test Case

Objective

Description

Passing Criteria

TL.1

Check the transport layer mapping using long transport layer test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid
  • jesd204_rx_dataout[(M*N*FRAMECLK_DIV)-1:0] 3

The jesd204_rx_int signal in jesd204b_ed.sv is tapped.

The rxframe_clk is used as the SignalTap II sampling clock.

  • The jesd204_rx_data_valid signal is asserted.
  • The long transport layer test pattern observed at jesd204_rx_dataout signal is correct
  • The jesd204_rx_int signal is deasserted.
3 M is the number of converters per device. N is the number of conversion bits per converter. FRAMECLK_DIV is the divider ratio on the frame_clk signal.
Level Two Title