AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

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ID 683135
Date 2/09/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12J4000 EVM Software Setup 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 733 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

1.2. Hardware Setup

This test uses a Stratix V Advanced Systems Development Kit with the TI ADC12J4000 daughter card module installed on the development board’s FMC connector.

Figure 1. Hardware Setup
  • The ADC12J4000 EVM derives power from the 5 V power adaptor.
  • The 3.76 GHz ADC device clock is sourced from the LMX2581 frequency synthesizer on the ADC12J4000 EVM.
  • The LMX2581 supplies 1.88 GHz clock to the LMK04828 clock generator on the ADC12J4000 EVM. The LMK04828 divides the 1.88 GHz input clock and distribute the 235 MHz device clock to the FPGA through the FMC connector.
  • For subclass 1, the LMK04828 system clock generator generates SYSREF pulses for the JESD204B IP core in the FPGA as well as the ADC12J4000 device.
Figure 2.  System DiagramThe system-level diagram shows how the different modules connect in this design. In this setup, where LMF=422, the data rate of transceiver lanes is 9.4 Gbps.


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