1.5. JESD204B IP Core and ADC Configurations
The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the ADC12J4000 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the ADC12J4000 operating conditions. The hardware checkout testing here implements the JESD204B IP core and ADC with the following parameter configuration.
| Configuration |
Setting |
||
|---|---|---|---|
| LMF |
124 |
222 |
422 |
| HD |
0 |
0 |
0 |
| S |
1 |
1 |
2 |
| N |
15 |
15 |
15 |
| N’ |
16 |
16 |
16 |
| CS |
1 |
1 |
1 |
| CF |
0 |
0 |
0 |
| Decimation Factors 4 |
16 |
8 |
4 |
| DDR 5 |
1 |
1 |
1 |
| P54 6 |
1 |
1 |
1 |
| ADC Device Clock (MHz) |
3760 |
3760 |
3760 |
| ADC Sampling Clock (MHz) |
235 |
470 |
940 |
| FPGA Device Clock (MHz) 7 |
235 |
235 |
235 |
| FPGA Management Clock (MHz) |
100 |
100 |
100 |
| FPGA Frame Clock (MHz) 8 |
235 |
235 |
235 |
| FPGA Link Clock (MHz) 8 |
235 |
235 |
235 |
| Character Replacement |
Enabled |
Enabled |
Enabled |
| Data Pattern |
Long Transport Layer test pattern |
Long Transport Layer test pattern |
Long Transport Layer test pattern |
4 This is not a JESD204B IP core parameter. Refer to the ADC12J4000 datasheet for more details.
5 Serial line rate. This is not a JESD204B IP core parameter. Refer to the ADC12J4000 datasheet for more details.
6 Enable 5/4 PLL to increase the line rate by 1.25x. This is not a JESD204B IP core parameter. Refer to the ADC12J4000 datasheet for more details.
7 The device clock is used to clock the transceiver.
8 The frame clock and link clock is derived from the device clock using an internal PLL.