SDI II Intel® FPGA IP User Guide

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ID 683133
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Manual Adaptation Mode 7.1.3.3. TX EQ Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon-MM Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

10. Document Revision History for the SDI II Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.04.04 22.1 19.2.1
  • Updated Intel® Agilex™ F-tile details for 12G-SDI, Triple Rate (up to 3G), Multi Rate (Up to 12G-SDI) TX and Multi Rate (Up to 12G-SDI) RX in SDI II Standard Support table.
  • Updated details for ALMs Needed, Dedicated Logic Registers and Block Memory Bits in Resource Utilization for Each Video Standard for Intel Agilex F-tile Devices table.
  • Updated SDI II IP Core Parameters table as below:
    • Removed support for 12G-SDI single rate and added support for Multi rate (up to 12G).
    • Updated note for Rx core clock to use the same clock as i_csr_clk port on F-tile Dynamic Reconfiguration Suite IP.
  • Added note for the below signals in Receiver Protocol Signals—Synchronous to rx_coreclk table:
    • rx_f
    • rx_v
    • rx_h
  • Updated Summary for Minimum System PLL Output Frequency for Different SDI Modes table as below:
    • Removed support for 12G-SDI single rate.
    • Added support for Triple rate SDI and Multi rate SDI.
  • Added note in System PLL Clocking Mode section.
  • Updated the codeblock in RX Manual Adaptation Mode section.
  • Added two new sections under the Handling Transceiver in Intel Agilex F-tile Devices section:
    • Unused Transceiver Tiles
    • Dynamic Reconfiguration
    • SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
2022.02.16 21.4 19.2.0
  • Added the Intel® Agilex™ F-tile device's preliminary support level details in the Intel Device Family Support table.
  • Added Intel® Agilex™ F-tile device details and a column for 12G-SDI under Single Rate mode in SDI II Standard Support table.
  • Added Resource Utilization for Each Video Standard for Intel Agilex F-tile Devices table.
  • Added Intel® Agilex™ F-tile device details in Recommended Speed Grades table.
  • Renamed SDI II to SDI II Intel FPGA IP in Launching IP Catalog section.
  • Updated the following in the Parameterizing the IP Core section:
    • Added related information for SDI II Intel Agilex FPGA IP Design Example User Guide for more information on Agilex.
  • Updated the Generating a Design Example and Simulation Testbench section with Intel® Agilex™ F-tile directory details.
  • Updated the following in Compiling the SDI II IP Core Design section:
    • Added the Intel® Agilex™ F-tile directory details.
    • Added related information for SDI II Intel Agilex FPGA IP Design Example User Guide for more information on Agilex.
  • Updated the following in the SDI II IP Core Parameters table:
    • Added a note for the Intel® Agilex™ device that supports a 12G-SDI single rate as a preliminary feature for the Video Standard parameter under Configurations Options.
    • Updated note that Intel® Agilex™ F-tile devices do not support the given parameter options.
    • Added note for Intel® Agilex™ F-tile value details for Rx core clock (rx_coreclk) frequency parameter under Receiver Options.
  • Added support for Intel® Agilex™ F-tile device in SDI II IP Core Functional Description section and Transceiversub-section.
  • Renamed the below column headings in Oversampling Requirement table:
    • Dual Rate to Dual-Rate
    • Triple Rate to Triple-Rate
    • Multi Rate to Multi-Rate
  • Added a note for Intel® Agilex™ Device in Detect 1 and 1/1.001 Rates section.
  • Updated the following in the Reset and Clock Signals table:
    • Added Intel® Agilex™ F-tile device support for tx_rst signal.
    • Updated a note on the Intel® Agilex™ F-tile device configuration status as applicable or not applicable for the following signals:
      • pll_powerdown_in
      • pll_powerdown_out
      • trig_rst_ctrl
      • xcvr_rxclk
      • tx_coreclk
      • tx_coreclk_hd
      • rx_coreclk_hd
      • rx_clkin
      • rx_clkin_b
      • xcvr_rxclk
      • xcvr_refclk
      • xcvr_refclk_alt
      • tx_clkout
      • rx_clkout
    • Added a note for the Intel® Agilex™ device in the rx_coreclk signal to set the clock frequency range between 100 MHz and 156.25 MHz. Intel recommends sharing the same clock as the port from the F-tile dynamic reconfiguration suite IP i_csr_clk core.
  • Updated the below figure captions:
    • TX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 to TX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices
    • RX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 to RX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices
  • Updated the following in Transmitter Protocol Signals—Synchronous to tx_pclk table:
    • Updated 12G to 12G-SDI for tx_ln_b signal.
    • Added support for Intel® Agilex™ F-tile devices for tx_dataout signal.
    • Update note as not applicable for Intel® Agilex™ F-tile devices for tx_std_out signal.
  • Updated the following in the Receiver Protocol Signals—Synchronous to rx_coreclk table:
    • Added note for rx_coreclk_is_ntsc_paln that the signal is not applicable for Agilex device family.
    • Updated a note on the Intel® Agilex™ F-tile device configuration status as applicable or not applicable for the following signals:
      • rx_std_in
      • rx_std(for transceiver only configurations)
  • Updated the following in the Receiver Protocol Signals—Synchronous to rx_clkout or xcvr_rxclk table:
    • Added support for Intel® Agilex™ F-tile device for rx_datain signal.
    • Updated the note on the Intel® Agilex™ F-tile device configuration status as not applicable for the following signals:
      • rx_datain_b
      • rx_datain_valid
      • rx_datain_valid_b
      • rx_trs_loose_lock_in
      • rx_trs_loose_lock_in_b
      • rx_trs_in
      • rx_trs_loose_lock_out_b
  • Updated the following in the Transceiver Signals table:
    • Updated a note on the Intel® Agilex™ F-tile device support and configuration status as not applicable for the following signals:
      • xcvr_refclk_sel
      • tx_pll_locked
      • tx_pll_locked_alt
      • reconfig_to_xcvr
      • reconfig_to_xcvr_b
      • reconfig_from_xcvr
      • reconfig_from_xcvr_b
    • Added support for Agilex F-tile devices for rx_sdi_reconfig_done signal.
    • Updated a note on the Intel® Agilex™ F-tile device support and configuration status as applicable for the following signals:
      • rx_ready
      • gxb_ltr
      • gxb_ltd
  • Added Handling Transceiver in Intel® Agilex™ F-tile Devices section.
  • Renamed Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 section to Design Examples for Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10, and Intel® Agilex™ F-tile Devices.
  • Added related information for SDI II Intel Agilex FPGA IP Design Example User Guide for more information on Agilex in Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices section.
2021.10.08 21.3 19.1.1
  • Edited the Brief Information About the SDI II Intel® FPGA IP Core table:
    • Changed ModelSim* - Intel® FPGA Edition to Questa*-Intel® FPGA Edition .
    • Changed ModelSim* - Intel® FPGA Starter Edition to ModelSim SE* .
    • Removed NCSim.
2021.08.27 20.2 19.1.1
  • Removed Ncsim from Design Tools in Brief Information About the SDI II Intel FPGA IP Core table.
  • Edited the Video Standard in EAV and SAV Sequences table. Changed the terminology for data interleaving from Streams Interleaved to Multiplex Type.
  • Added the description in Detect Format section with information about how rx_format report the detected transport format.
  • Edited the Description in Transmitter Protocol Signals—Synchronous to tx_pclk table and Receiver Protocol Signals—Synchronous to rx_clkout or xcvr_rxclk table for tx_std and rx_std signal.
    • Changed the terminology for data interleaving from Streams Interleaved to Multiplex Type.
    • Added figures for Single-link 6G-SDI 10-bit Multiplex and 6G-SDI 10-bit multiplex.
2020.10.01 20.2 19.1.1
  • Added the Unused Transceiver Channels section that provides guideline to preserve unused transceiver channels.
  • Updated the description for the rx_coreclk clock in the SDI II IP Core Resets and Clocks section and added the Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices section with information about the limitation on transceiver reference clock pin connection to the core logic in specific channels in a transceiver bank.
2019.08.08 19.1 19.1 Edited a bad character in the Merging Simplex Mode Transceiver in the Same Channel section.
2019.04.01 19.1 19.1
  • Added support for Intel® Stratix® 10 L-tile devices. Support for both Intel® Stratix® 10 L-tile and H-tile devices are final.
  • Edited the description for the tx_trs signal in the Transmitter Protocol Signals section. Removed the line "For use in LN, CRC, or payload ID insertion". This signal is always required for all 6G-SDI and 12G-SDI designs.
  • Edited the description for the tx_datain_valid and tx_datain_valid_b signals in the Transmitter Protocol Signals section. This signal can be driven by user logic or by the tx_dataout_valid_b signal.
  • Edited the description for the rx_coreclk signal in the Core Resets and Clocks section. Added information that this clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.
  • Added steps for implementing TX PLL and reference clock switching in the Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices section.
2018.09.24 18.1 18.1
  • Revised the resource utilization data information for version 18.1.
  • Added guidelines about how to use duplex mode with the multi-rate and triple-rate presets for Intel® Arria® 10 devices in the Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices section.
  • Added the Unconstrained Clocks in SDI Multi-Rate RX Preset Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices section under SDI II IP Core Design Considerations chapter.
  • Renamed Potential Routability Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices to Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices.
2018.05.07 18.0 18.0
  • Renamed Intel FPGA SDI II IP core to SDI II IP core as part of standardizing and rebranding exercise.
  • Renamed hard transceiver to Native PHY IP for better clarity.
  • Added support for Intel® Cyclone® 10 GX device.
  • Added support for Xcelium* Parallel simulator.
  • Revised the resource utilization data information for version 18.0.
  • Added <variation name>.qsys and <variation name>.ip in the generated files list in the SDI II IP Core Component Files section.
  • Added new parameter, Rx core clock (rx_coreclk) frequency. This parameter is available only when you select Multi rate (up to 12G) and Receiver or Bidirectional direction in the Intel® Quartus® Prime Pro Edition software.
  • Updated the description for the rx_coreclk signal. You can select either 148.5/148.35 MHz or 297.0/296.70 MHz for Multi rate (up to 12G) mode using Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
  • Updated the description for the rx_coreclk_is_ntsc_paln signal to add 297.0 MHz and 296.70 MHz options.
  • Updated the description for the tx_ln and tx_ln_b signals to include that for Payload ID insertion, these signals must be driven with valid values.
  • Updated the description for the tx_line_f0 and tx_line_f1 signals to include that the line number must be valid and cannot be set to 0.
  • Edited the Triple Rate Transmit Clocking Scheme timing diagram in the Clock Enable Generator section. The valid signal for the SD-SDI standard should deassert at the rising edge of the second clock cycle and not at the falling edge of the first clock cycle.
  • Renamed Potential Routability Issue During Fitter Stage in Intel® Arria® 10 Devices topic to Potential Routability Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices. Potential routability problem affects Intel® Cyclone® 10 GX devices too.
Date Version Changes
November 2017 2017.11.06
  • Renamed SDI II IP core to Intel FPGA SDI II as per Intel rebranding.
  • Changed the term Qsys to Platform Designer
  • Added preliminary support for Intel® Stratix® 10 (H-Tile) devices.
  • Revised the resource utilization data information for version 17.1.
  • Added guidelines on how to change the RX CDR reference clock value for higher clock frequencies.
  • Added information about Intel® Stratix® 10 in the Intel FPGA SDI II IP Core Parameters and Intel FPGA SDI II IP Core Signals sections.
  • Moved information about the Intel FPGA SDI II design example parameters to the respective design example user guides.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Revised the resource utilization data and added recommended speed grades information for version 17.0.
  • Clarified the description for the tx_trs signal. The first word of both EAV and SAV TRSs could mean two tx_pclk cycles or one tx_pclk cycle depending on the mode selected.
  • Added an example of 16-bit rx_format for 6G-SDI and 12G-SDI interfaces.
  • Added additional information about the overwrite Payload ID feature.
  • Edited the multi-rate (up to 12G-SDI) transmitter and receiver data path block diagrams to include the sync bit insertion and removal blocks.
  • Updated the SMPTE standards to the latest naming convention.
  • Added a note in the Transceiver Reconfiguration Controller section that the transceiver reconfiguration controller only reconfigures the TX transceiver if you are performing TX clock switching.
December 2016 2016.12.20
  • Added detailed description for tx_datain and rx_dataout signals about 6G-SDI and 12G-SDI interfaces.
  • Added information about image mapping for 6G-SDI and 12G-SDI interfaces.
  • Added information for rx_dataout_valid signal that the 1H4L 1H5L cadence for SD-SDI repeats indefinitely in an ideal case but in a typical scenario the cadence shift periodically (for instance, 1H4L 1H5L 1H5L 1H4L).
  • Updated rx_format information to include that for 6G-SDI or 12G-SDI interfaces, each of the 20-bit interface reports its own detected format.
  • Added information for pll_powerdown_in signal that sharing Tx PLLs for designs that also implement dynamic reconfiguration require XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.
October 2016 2016.10.31
  • Restructured the chapters.
  • Added information for the new Design Example parameters.
  • Removed all Arria 10 design example related information. For more information about Arria 10 design examples, refer to the SDI II IP Core Design Example User Guide.
  • Added clocking diagrams for Arria 10 devices and the V series devices—Arria V, Cyclone V, and Stratix V.
  • Added guideline to overcome potential routability issue during Fitter stage.
May 2016 2016.05.02
  • Added new option, fPLL, for the Arria 10 TX PLL parameter and removed the ATX PLL option.
  • Added estimated run-time settings for the different SDI II video standards.
  • Added guideline for transceiver handling. The transceiver handling guidelines differ for Arria 10 devices and the V series devices—Arria V, Cyclone V, and Stratix V.
  • Added new transceiver signals:
    • rx_analogreset_ack
    • tx_analogreset_ack
    • rx_cal_busy
    • pll_powerdown
    • xcvr_rxclk
    • xcvr_rxclk_b
    • rst_tx_phy
  • Added a new receiver signals: rx_datain and rx_datain_valid.
  • Removed these signals: rx_pll_locked and rx_pll_locked_b. These signals are redundant and no longer required after the switch to Native PHY.
  • Updated the design example directory.
  • Added links to archived versions of the SDI II IP Core User Guide.
November 2015 2015.11.02
  • Added information that the rx_format signal for each stream reports its own detected format for 6G-SDI and 12G-SDI interfaces.
  • Added information about 3 new interface signals for Arria V, Cyclone V, Stratix V devices: rx_trs_in, pll_powerdown_in, and pll_powerdown_out
  • Added reconfiguration management parameters for Arria 10 devices: VIDEO_STANDARD, ED_TXPLL_SWITCH, and XCVR_RCFG_IF_TYPE.
  • Added descriptions for the SDI presets available in the Arria 10 Transceiver Native PHY IP core.
May 2015 2015.05.04
  • Changed the resource utilization table to include data for each SDI standard and updated the data for version 15.0.
  • Added new multi-rate data path block diagrams for transmitter and receiver.
  • Added new information about inserting sync bits.
  • Renamed the term video payload ID (VPID) to payload ID as per SMPTE specification.
  • Renamed Level A to HD-SDI dual link and Level B to 3G-SDI (level B).
  • Updated the following new parameter options:
    • Added new video standard Multi rate (up to 12G) for Arria 10 devices.
    • Added TX PLL reference clock switching option for Dynamic Tx clock switching parameter.
  • Added a note for the interface signals to indicate that multi-rate (up to 12G) mode requires 4 streams and the rest require one stream.
  • Added a new parameter for Reconfiguration Management: XCVR_TX_PLL_SEL.
  • Added information for multi standard support including 6G-SDI and 12G-SDI.
  • Added the multi standard (including 6G-SDI and 12G-SDI) information for the following signals:
    • tx_enable_ln
    • tx_std
    • tx_datain
    • tx_datain_valid
    • tx_ln_b
    • tx_dataout
    • tx_dataout_valid
    • tx_vpid_byte(1-4)_b
    • rx_std
    • rx_dataout_valid
    • rx_format
    • rx_ln_b
    • rx_vpid_byte(1-4)_b
    • rx_vpid_checksum_error_b
  • Added information that the following signals are not applicable for Arria 10 devices:
    • rx_coreclk_hd
    • rx_clkin
    • rx_clkin_b
    • rx_rst_proto_in
    • rx_rst_proto_in_b
January 2015 2015.01.23
  • Updated the resource utilization table for version 14.1.
  • Changed the names of the following parameters for receiver options:
    • Convert Level A to Level B (SMPTE 372M) changed to Convert HD-SDI dual link to 3G-SDI (level B).
    • Convert Level B to Level A (SMPTE 372M) changed to Convert 3G-SDI (level B) to HD-SDI dual link.
  • Edited information about rx_format signal, which now reports video transport format instead of picture format. The signal reports 3G Level A RGB or YCbCr 4:4:4 format.
August 2014 2014.08.18
  • Added support for Arria 10 devices.
  • Revised the resource utilization table with information about ALM needed and primary and secondary logic registers.
  • Added information related to Arria 10 devices.
    • Added new parameters for Example Design Options.

    • Added new transceiver information—for the Arria 10 devices, the SDI II IP core no longer provides the transceiver, and the TX PLL is no longer wrapped in the transceiver PHY. You must generate the transceiver and the TX PLL separately.

    • Added new transceiver signals: rx_ready, gxb_ltr, gxb_ltd, rx_ready_b, gxb_ltr_b, gxb_ltd_b, and trig_rst_ctrl.
  • Added information for the newly added Arria 10 design example.
    • Added design example entity and simulation testbench diagram.
    • Added connecting input signals: rx_manual and rx_is_lockedtodata.
    • Added information about transceiver reconfiguration controller— for Arria 10 designs, the reconfiguration interface is integrated into the Arria 10 Native PHY instance and TX PLL.
    • Added transceiver reconfiguration controller signals.
  • Added information about IP catalog and removed information about MegaWizard Plug-In Manager.

July 2013

2013.06.28

  • Added a section for each new feature:
    • Tx PLL Dynamic Switching
    • SMPTE RP168 Switching
    • SD Optional 20-bit Interface for Dual/Triple Rate
  • Added information about a new submodule, Convert SD Bits.
  • Added information about a new parameter, SD Interface Bit Width.
  • Added more information about the design example components—Reconfiguration Management, Reconfiguration Router, Avalon-MM Translators.
  • Added more information about the design example operation:
    • Transceiver Dynamic Reconfiguration
    • Expanding to Multiple Channels
  • Updated the protocol and transceiver signals table.
  • Updated the resource utilization table.

November 2012

2012.11.15

Initial release.

Level Two Title