Visible to Intel only — GUID: iga1401398649150
Ixiasoft
Visible to Intel only — GUID: iga1401398649150
Ixiasoft
23.4.3. Register Map
The Intel-provided HAL device driver accesses the device registers directly. If you are writing a device driver, and the HAL driver is active for the same device, your driver will conflict and fail to operate correctly.
The table below shows the register map for the 32-bit timer. The interval timer core uses native address alignment. For example, to access the control register value, use offset 0x4.
Offset | Name | R/W | Description of Bits | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
15 | ... | 4 | 3 | 2 | 1 | 0 | |||||
0 | status | RW | (1) | RUN | TO | ||||||
1 | control | RW | (1) | STOP | START | CONT | ITO | ||||
2 | periodl | RW | Timeout Period – 1 (bits [15:0]) | ||||||||
3 | periodh | RW | Timeout Period – 1 (bits [31:16]) | ||||||||
4 | snapl | RW | Counter Snapshot (bits [15:0]) | ||||||||
5 | snaph | RW | Counter Snapshot (bits [31:16]) | ||||||||
Notes :
|
For more information about native address alignment, refer to the Memory-Mapped Interfaces section of the Quartus® Prime Standard Edition User Guide: Platform Designer and the Quartus® Prime Pro Edition User Guide: Platform Designer.
Offset | Name | R/W | Description of Bits | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
15 | ... | 4 | 3 | 2 | 1 | 0 | |||||
0 | status | RW | (1) | RUN | TO | ||||||
1 | control | RW | (1) | STOP | START | CONT | ITO | ||||
2 | period_0 | RW | Timeout Period – 1 (bits [15:0]) | ||||||||
3 | period_1 | RW | Timeout Period – 1 (bits [31:16]) | ||||||||
4 | period_2 | RW | Timeout Period – 1 (bits [47:32]) | ||||||||
5 | period_3 | RW | Timeout Period – 1 (bits [63:48]) | ||||||||
6 | snap_0 | RW | Counter Snapshot (bits [15:0]) | ||||||||
7 | snap_1 | RW | Counter Snapshot (bits [31:16]) | ||||||||
8 | snap_2 | RW | Counter Snapshot (bits [47:32]) | ||||||||
9 | snap_3 | RW | Counter Snapshot (bits [63:48]) | ||||||||
Notes :
|
status Register
The status register has two defined bits.
Bit | Name | R/W/C | Description |
---|---|---|---|
0 | TO | R/WC | The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a host peripheral. Write 0 or 1 to the status register to clear the TO bit. |
1 | RUN | R | The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by a write operation to the status register. |
control Register
The control register has four defined bits.
Bit | Name | R/W/C | Description |
---|---|---|---|
0 | ITO | RW | If the ITO bit is 1, the interval timer core generates an IRQ when the status register’s TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs. |
1 | CONT | RW | The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit. |
2 | START (1) | W | Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect. |
3 | STOP (1) | W | Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect. |
Notes :
|
period_n Registers
The period_n registers together store the timeout period value. The internal counter is loaded with the value stored in these registers whenever one of the following occurs:
- A write operation to one of the period_n register
- The internal counter reaches 0
The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle.
Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.
snap_n Registers
A host peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.