There are three ways to access the QSPI flash in SDM-based devices when you migrate from control block-based devices in flash access and remote system update. Intel recommends that you use the Mailbox Client Intel® FPGA IP for both flash access and remote system update, as shown in the following figure.

When the configuration flash is connected to the SDM I/O pins, Intel also recommends that you use the Mailbox Client Intel® FPGA IP.

You can use the Mailbox Client Intel® FPGA IP to access the QSPI flash which is connected to the SDM I/O and perform the remote system update in supported SDM-based devices. Commands and configuration images are sent to the host controller. The host controller then translates the command into Avalon® memory-mapped format and sends it to the Mailbox Client Intel® FPGA IP. The Mailbox Client Intel® FPGA IP drives the commands/data and receives the responses from the SDM. The SDM writes the configuration images to the QSPI flash device. The Mailbox Client Intel® FPGA IP is also an Avalon® memory-mapped slave component. The host controller can be an Avalon® master, such as JTAG master, a Nios® II processor, PCIe* , a custom logic, or Ethernet IP.

You can use the Mailbox Client Intel® FPGA IP to command the SDM to perform reconfiguration with the new/updated image in QSPI flash devices. Intel recommends that you use the Mailbox Client Intel® FPGA IP in new designs because this IP can access QSPI flash and perform RSU operation. This IP is supported in all supported SDM-based devices, which eases design migration between them. Refer to the Supported Devices by Architecture Type table in the Introduction section for details on supported SDM-based devices.

You can only use the Serial Flash Mailbox Client Intel® FPGA IP to access QSPI flash connected to SDM I/O in the Intel® Stratix® 10 devices. Commands and configuration images are sent to the host controller. The host controller then translates the command into Avalon® memory-mapped format and sends it to the Serial Flash Mailbox Client Intel® FPGA IP. The Serial Flash Mailbox Client Intel® FPGA IP then sends the commands/data and receives responses from the SDM. The SDM writes the configuration images to the QSPI flash device. The Serial Flash Mailbox Client Intel® FPGA IP is an Avalon® memory-mapped slave component. Hence, the host controller can be an Avalon® master, such as a JTAG master, Nios® II processor, PCI Express* ( PCIe* ), a custom logic, or Ethernet IP.

The Mailbox Client Intel® FPGA IP is required to perform remote system update operation. Hence, the Serial Flash Mailbox Client Intel® FPGA IP is not recommended in newer designs as it only supports Intel® Stratix® 10 devices and can only be used to access QSPI flash devices.

The Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP provides a communication channel between your custom logic and the secure device manager (SDM) in Intel Agilex® 7 devices. You can use this IP to send command packets and receive response packets from the SDM peripheral modules, including QSPI. The SDM writes the new images to the QSPI flash device and then reconfigures the Intel Agilex® 7 device from the new or updated image.

The Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP uses the Avalon® streaming interface. You must use a host controller with Avalon® streaming interface to control the IP. The Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP has faster data streaming than the Mailbox Client Intel® FPGA IP. However, this IP does not support Intel® Stratix® 10 devices, which means you cannot migrate your design directly from Intel® Stratix® 10 devices to Intel Agilex® 7 devices.