The following figure shows the IPs used in flash access and remote system update operation on supported control block-based devices, as well as the interfaces of each IPs. Refer to the Supported Devices by Architecture Type table in the Introduction section for details on supported control block-based devices.

You can use the Generic Serial Flash Interface Intel® FPGA IP and QUAD Serial Peripheral Interface (SPI) Controller II to perform the flash access, similarly the Remote Update Intel® FPGA IP is used to perform the RSU operation. Intel recommends that you use the Generic Serial Flash Interface Intel® FPGA IP as this IP is newer and can be used with any quad serial peripheral Interface (QSPI) flash devices.

The flash devices can be connected to either a dedicated Active Serial (AS) pins or the general purpose I/O (GPIO) pins. If you want to use the QSPI flash devices for FPGA configuration and to store user data, the QSPI device must be connected to the dedicated active serial memory interface (ASMI) pin. In an active serial configuration, the MSEL pin setting is sampled when the FPGA is powered up. The control block receives QSPI flash data from the configuration devices and configures the FPGA.