Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 12/03/2024
Public

Visible to Intel only — GUID: sfo1410068286284

Ixiasoft

Document Table of Contents

10.2.1. Cortex®-A9 MPU Subsystem with System Interconnect

This block diagram shows a dual‑core MPU subsystem in the context of the HPS, with the L2 cache. The L2 cache can access either the system interconnect or the SDRAM.

Figure 23.  Cortex®-A9 MPU Subsystem with Interconnect Block Diagram