Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

2.4.2. HPS Peripheral Region Address Map

Each peripheral slave interface has a dedicated address range in the peripheral region. The table below lists the base address and address range size for each slave.

Table 4.  Peripheral Region Address Map

Slave Identifier

Description

Base Address

Size

STM

Space Trace Macrocell

0xFC000000

48 MB

DAP

Debug Access Port

0xFF000000

2 MB

LWFPGASLAVES

FPGA slaves accessed with lightweight HPS-to-FPGA bridge

0xFF200000

2 MB

LWHPS2FPGAREGS

Lightweight HPS-to-FPGA bridge global programmer's view (GPV) registers

0xFF400000

1 MB

HPS2FPGAREGS

HPS-to-FPGA bridge GPV registers

0xFF500000

1 MB

FPGA2HPSREGS

FPGA-to-HPS bridge GPV registers

0xFF600000

1 MB

EMAC0

Ethernet MAC 0

0xFF700000

8 KB

EMAC1

Ethernet MAC 1

0xFF702000

8 KB

SDMMC

SD/MMC

0xFF704000

4 KB

QSPIREGS

Quad SPI flash controller registers

0xFF705000

4 KB

FPGAMGRREGS

FPGA manager registers

0xFF706000

4 KB

ACPIDMAP

ACP ID mapper registers

0xFF707000

4 KB

GPIO0

GPIO 0

0xFF708000

4 KB

GPIO1

GPIO 1

0xFF709000

4 KB

GPIO2

GPIO 2

0xFF70A000

4 KB

L3REGS

L3 interconnect GPV

0xFF800000

1 MB

NANDDATA

NAND flash controller data

0xFF900000

64 KB

QSPIDATA

Quad SPI flash data

0xFFA00000

1 MB

USB0

USB 2.0 OTG 0 controller registers

0xFFB00000

256 KB

USB1

USB 2.0 OTG 1 controller registers

0xFFB40000

256 KB

NANDREGS

NAND flash controller registers

0xFFB80000

64 KB

FPGAMGRDATA

FPGA manager configuration data

0xFFB90000

4 KB

CAN0

CAN 0 controller registers

0xFFC00000

4 KB

CAN1

CAN 1 controller registers

0xFFC01000

4 KB

UART0

UART 0

0xFFC02000

4 KB

UART1

UART 1

0xFFC03000

4 KB

I2C0

I2C controller 0

0xFFC04000

4 KB

I2C1

I2C controller 1

0xFFC05000

4 KB

I2C2

I2C controller 2

0xFFC06000

4 KB

I2C3

I2C controller 3

0xFFC07000

4 KB

SPTIMER0

SP Timer 0

0xFFC08000

4 KB

SPTIMER1

SP Timer 1

0xFFC09000

4 KB

SDRREGS

SDRAM controller subsystem registers

0xFFC20000

128 KB

OSC1TIMER0

OSC1 Timer 0

0xFFD00000

4 KB

OSC1TIMER1

OSC1 Timer 1

0xFFD01000

4 KB

L4WD0

Watchdog Timer 0

0xFFD02000

4 KB

L4WD1

Watchdog Timer 1

0xFFD03000

4 KB

CLKMGR

Clock manager

0xFFD04000

4 KB

RSTMGR

Reset manager

0xFFD05000

4 KB

SYSMGR

System manager

0xFFD08000

16 KB

DMANONSECURE

DMA nonsecure registers

0xFFE00000

4 KB

DMASECURE

DMA secure registers

0xFFE01000

4 KB

SPIS0

SPI slave 0

0xFFE02000

4 KB

SPIS1

SPI slave 1

0xFFE03000

4 KB

SPIM0

SPI master 0

0xFFF00000

4 KB

SPIM1

SPI master 1

0xFFF01000

4 KB

SCANMGR

Scan manager registers

0xFFF02000

4 KB

ROM

Boot ROM

0xFFFD0000

64 KB

MPU

MPU registers

0xFFFEC000

8 KB

MPUL2

MPU L2 cache controller registers

0xFFFEF000

4 KB

OCRAM

On-chip RAM

0xFFFF0000

64 KB