Visible to Intel only — GUID: sfo1410067633182
Ixiasoft
Visible to Intel only — GUID: sfo1410067633182
Ixiasoft
2.4.1. HPS Address Spaces
The following table shows the HPS address spaces and their sizes.
Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space has the peripheral, FPGA slaves, SDRAM window, and boot regions.
The following figure shows the relationships between the HPS address spaces. The figure is not to scale.
The window regions provide access to other address spaces. The thin black arrows indicate which address space is accessed by a window region (arrows point to accessed address space). For example, accesses to the ACP window in the L3 address space map to a 1 GB region of the MPU address space.
The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to “MPU Address Space”.
The ACP window can be mapped to any 1 GB region in the MPU address space (blue vertical bidirectional arrow), on gigabyte-aligned boundaries.
Region Name |
Base Address |
Size |
---|---|---|
FPGA slaves |
0xC0000000 |
960 MB |
Peripheral |
0xFC000000 |
64 MB |
Lightweight FPGA slaves |
0xFF200000 |
2 MB |