Visible to Intel only — GUID: sfo1410068312775
Ixiasoft
Visible to Intel only — GUID: sfo1410068312775
Ixiasoft
10.3.12.2.1. GIC Interrupt Map for the Cyclone V SoC HPS
GIC Interrupt Number |
Source Block |
Interrupt Name |
Combined Interrupts |
Triggering |
---|---|---|---|---|
32 |
CortexA9_0 |
cpu0_parityfail | This interrupt combines the interrupts named: cpu0_parityfail_*. |
Edge |
33 |
CortexA9_0 |
cpu0_parityfail_BTAC | — |
Edge |
34 |
CortexA9_0 |
cpu0_parityfail_GHB | — |
Edge |
35 |
CortexA9_0 |
cpu0_parityfail_I_Tag | — |
Edge |
36 |
CortexA9_0 |
cpu0_parityfail_I_Data | — |
Edge |
37 |
CortexA9_0 |
cpu0_parityfail_TLB | — |
Edge |
38 |
CortexA9_0 |
cpu0_parityfail_D_Outer | — |
Edge |
39 |
CortexA9_0 |
cpu0_parityfail_D_Tag | — |
Edge |
40 |
CortexA9_0 |
cpu0_parityfail_D_Data | — |
Edge |
41 |
CortexA9_0 |
cpu0_deflags0 | — |
Level |
42 |
CortexA9_0 |
cpu0_deflags1 | — |
Level |
43 |
CortexA9_0 |
cpu0_deflags2 | — |
Level |
44 |
CortexA9_0 |
cpu0_deflags3 | — |
Level |
45 |
CortexA9_0 |
cpu0_deflags4 | — |
Level |
46 |
CortexA9_0 |
cpu0_deflags5 | — |
Level |
47 |
CortexA9_0 |
cpu0_deflags6 | — |
Level |
48 |
CortexA9_1 |
cpu1_parityfail | This interrupt combines the interrupts named: cpu0_parityfail_*. |
Edge |
49 |
CortexA9_1 |
cpu1_parityfail_BTAC | — |
Edge |
50 |
CortexA9_1 |
cpu1_parityfail_GHB | — |
Edge |
51 |
CortexA9_1 |
cpu1_parityfail_I_Tag | — |
Edge |
52 |
CortexA9_1 |
cpu1_parityfail_I_Data | — |
Edge |
53 |
CortexA9_1 |
cpu1_parityfail_TLB | — |
Edge |
54 |
CortexA9_1 |
cpu1_parityfail_D_Outer | — |
Edge |
55 |
CortexA9_1 |
cpu1_parityfail_D_Tag | — |
Edge |
56 |
CortexA9_1 |
cpu1_parityfail_D_Data | — |
Edge |
57 |
CortexA9_1 |
cpu1_deflags0 | — |
Level |
58 |
CortexA9_1 |
cpu1_deflags1 | — |
Level |
59 |
CortexA9_1 |
cpu1_deflags2 | — |
Level |
60 |
CortexA9_1 |
cpu1_deflags3 | — |
Level |
61 |
CortexA9_1 |
cpu1_deflags4 | — |
Level |
62 |
CortexA9_1 |
cpu1_deflags5 | — |
Level |
63 |
CortexA9_1 |
cpu1_deflags6 | — |
Level |
64 |
SCU |
scu_parityfail0 | — |
Edge |
65 |
SCU |
scu_parityfail1 | — |
Edge |
66 |
SCU |
scu_ev_abort | — |
Edge |
67 |
L2‑Cache |
l2_ecc_byte_wr_IRQ | — |
Edge |
68 |
L2‑Cache |
l2_ecc_corrected_IRQ | — |
Edge |
69 |
L2‑Cache |
l2_ecc_uncorrected_IRQ | — |
Edge |
70 |
L2‑Cache |
l2_combined_IRQ | This interrupt combines: DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR. |
Level |
71 |
DDR |
ddr_ecc_error_IRQ | — |
Level |
72 |
FPGA |
FPGA_IRQ0 | — |
Level or Edge |
73 |
FPGA |
FPGA_IRQ1 | — |
Level or Edge |
74 |
FPGA |
FPGA_IRQ2 | — |
Level or Edge |
75 |
FPGA |
FPGA_IRQ3 | — |
Level or Edge |
76 |
FPGA |
FPGA_IRQ4 | — |
Level or Edge |
77 |
FPGA |
FPGA_IRQ5 | — |
Level or Edge |
78 |
FPGA |
FPGA_IRQ6 | — |
Level or Edge |
79 |
FPGA |
FPGA_IRQ7 | — |
Level or Edge |
80 |
FPGA |
FPGA_IRQ8 | — |
Level or Edge |
81 |
FPGA |
FPGA_IRQ9 | — |
Level or Edge |
82 |
FPGA |
FPGA_IRQ10 | — |
Level or Edge |
83 |
FPGA |
FPGA_IRQ11 | — |
Level or Edge |
84 |
FPGA |
FPGA_IRQ12 | — |
Level or Edge |
85 |
FPGA |
FPGA_IRQ13 | — |
Level or Edge |
86 |
FPGA |
FPGA_IRQ14 | — |
Level or Edge |
87 |
FPGA |
FPGA_IRQ15 | — |
Level or Edge |
88 |
FPGA |
FPGA_IRQ16 | — |
Level or Edge |
89 |
FPGA |
FPGA_IRQ17 | — |
Level or Edge |
90 |
FPGA |
FPGA_IRQ18 | — |
Level or Edge |
91 |
FPGA |
FPGA_IRQ19 | — |
Level or Edge |
92 |
FPGA |
FPGA_IRQ20 | — |
Level or Edge |
93 |
FPGA |
FPGA_IRQ21 | — |
Level or Edge |
94 |
FPGA |
FPGA_IRQ22 | — |
Level or Edge |
95 |
FPGA |
FPGA_IRQ23 | — |
Level or Edge |
96 |
FPGA |
FPGA_IRQ24 | — |
Level or Edge |
97 |
FPGA |
FPGA_IRQ25 | — |
Level or Edge |
98 |
FPGA |
FPGA_IRQ26 | — |
Level or Edge |
99 |
FPGA |
FPGA_IRQ27 | — |
Level or Edge |
100 |
FPGA |
FPGA_IRQ28 | — |
Level or Edge |
101 |
FPGA |
FPGA_IRQ29 | — |
Level or Edge |
102 |
FPGA |
FPGA_IRQ30 | — |
Level or Edge |
103 |
FPGA |
FPGA_IRQ31 | — |
Level or Edge |
104 |
FPGA |
FPGA_IRQ32 | — |
Level or Edge |
105 |
FPGA |
FPGA_IRQ33 | — |
Level or Edge |
106 |
FPGA |
FPGA_IRQ34 | — |
Level or Edge |
107 |
FPGA |
FPGA_IRQ35 | — |
Level or Edge |
108 |
FPGA |
FPGA_IRQ36 | — |
Level or Edge |
109 |
FPGA |
FPGA_IRQ37 | — |
Level or Edge |
110 |
FPGA |
FPGA_IRQ38 | — |
Level or Edge |
111 |
FPGA |
FPGA_IRQ39 | — |
Level or Edge |
112 |
FPGA |
FPGA_IRQ40 | — |
Level or Edge |
113 |
FPGA |
FPGA_IRQ41 | — |
Level or Edge |
114 |
FPGA |
FPGA_IRQ42 | — |
Level or Edge |
115 |
FPGA |
FPGA_IRQ43 | — |
Level or Edge |
116 |
FPGA |
FPGA_IRQ44 | — |
Level or Edge |
117 |
FPGA |
FPGA_IRQ45 | — |
Level or Edge |
118 |
FPGA |
FPGA_IRQ46 | — |
Level or Edge |
119 |
FPGA |
FPGA_IRQ47 | — |
Level or Edge |
120 |
FPGA |
FPGA_IRQ48 | — |
Level or Edge |
121 |
FPGA |
FPGA_IRQ49 | — |
Level or Edge |
122 |
FPGA |
FPGA_IRQ50 | — |
Level or Edge |
123 |
FPGA |
FPGA_IRQ51 | — |
Level or Edge |
124 |
FPGA |
FPGA_IRQ52 | — |
Level or Edge |
125 |
FPGA |
FPGA_IRQ53 | — |
Level or Edge |
126 |
FPGA |
FPGA_IRQ54 | — |
Level or Edge |
127 |
FPGA |
FPGA_IRQ55 | — |
Level or Edge |
128 |
FPGA |
FPGA_IRQ56 | — |
Level or Edge |
129 |
FPGA |
FPGA_IRQ57 | — |
Level or Edge |
130 |
FPGA |
FPGA_IRQ58 | — |
Level or Edge |
131 |
FPGA |
FPGA_IRQ59 | — |
Level or Edge |
132 |
FPGA |
FPGA_IRQ60 | — |
Level or Edge |
133 |
FPGA |
FPGA_IRQ61 | — |
Level or Edge |
134 |
FPGA |
FPGA_IRQ62 | — |
Level or Edge |
135 |
FPGA |
FPGA_IRQ63 | — |
Level or Edge |
136 |
DMA |
dma_IRQ0 | — |
Level |
137 |
DMA |
dma_IRQ1 | — |
Level |
138 |
DMA |
dma_IRQ2 | — |
Level |
139 |
DMA |
dma_IRQ3 | — |
Level |
140 |
DMA |
dma_IRQ4 | — |
Level |
141 |
DMA |
dma_IRQ5 | — |
Level |
142 |
DMA |
dma_IRQ6 | — |
Level |
143 |
DMA |
dma_IRQ7 | — |
Level |
144 |
DMA |
dma_irq_abort | — |
Level |
145 |
DMA |
dma_ecc_corrected_IRQ | — |
Level |
146 |
DMA |
dma_ecc_uncorrected_IRQ | — |
Level |
147 |
EMAC0 |
emac0_IRQ | This interrupt combines: sbd_intr_o and lpi_intr_o. |
Level |
148 |
EMAC0 |
emac0_tx_ecc_corrected_IRQ | — |
Level |
149 |
EMAC0 |
emac0_tx_ecc_uncorrected_IRQ | — |
Level |
150 |
EMAC0 |
emac0_rx_ecc_corrected_IRQ | — |
Level |
151 |
EMAC0 |
emac0_rx_ecc_uncorrected_IRQ | — |
Level |
152 |
EMAC1 |
emac1_IRQ | This interrupt combines: sbd_intr_o and lpi_intr_o. |
Level |
153 |
EMAC1 |
emac1_tx_ecc_corrected_IRQ | — |
Level |
154 |
EMAC1 |
emac1_tx_ecc_uncorrected_IRQ | — |
Level |
155 |
EMAC1 |
emac1_rx_ecc_corrected_IRQ | — |
Level |
156 |
EMAC1 |
emac1_rx_ecc_uncorrected_IRQ | — |
Level |
157 |
USB0 |
usb0_IRQ | — |
Level |
158 |
USB0 |
usb0_ecc_corrected_IRQ | — |
Level |
159 |
USB0 |
usb0_ecc_uncorrected_IRQ | — |
Level |
160 |
USB1 |
usb1_IRQ | — |
Level |
161 |
USB1 |
usb1_ecc_corrected_IRQ | — |
Level |
162 |
USB1 |
usb1_ecc_uncorrected_IRQ | — |
Level |
163 |
CAN0 |
can0_sts_IRQ | — |
Level |
164 |
CAN0 |
can0_mo_IRQ | — |
Level |
165 |
CAN0 |
can0_ecc_corrected_IRQ | — |
Level |
166 |
CAN0 |
can0_ecc_uncorrected_IRQ | — |
Level |
167 |
CAN1 |
can1_sts_IRQ | — |
Level |
168 |
CAN1 |
can1_mo_IRQ | — |
Level |
169 |
CAN1 |
can1_ecc_corrected_IRQ | — |
Level |
170 |
CAN1 |
can1_ecc_uncorrected_IRQ | — |
Level |
171 |
SDMMC |
sdmmc_IRQ | — |
Level |
172 |
SDMMC |
sdmmc_porta_ecc_corrected_IRQ | — |
Level |
173 |
SDMMC |
sdmmc_porta_ecc_uncorrected_IRQ | — |
Level |
174 |
SDMMC |
sdmmc_portb_ecc_corrected_IRQ | — |
Level |
175 |
SDMMC |
sdmmc_portb_ecc_uncorrected_IRQ | — |
Level |
176 |
NAND |
nand_IRQ | — |
Level |
177 |
NAND |
nandr_ecc_corrected_IRQ | — |
Level |
178 |
NAND |
nandr_ecc_uncorrected_IRQ | — |
Level |
179 |
NAND |
nandw_ecc_corrected_IRQ | — |
Level |
180 |
NAND |
nandw_ecc_uncorrected_IRQ | — |
Level |
181 |
NAND |
nande_ecc_corrected_IRQ | — |
Level |
182 |
NAND |
nande_ecc_uncorrected_IRQ | — |
Level |
183 |
QSPI |
qspi_IRQ | — |
Level |
184 |
QSPI |
qspi_ecc_corrected_IRQ | — |
Level |
185 |
QSPI |
qspi_ecc_uncorrected_IRQ | — |
Level |
186 |
SPI0 |
spi0_IRQ | This interrupt combines: ssi_txe_intr, ssi_txo_intr, ssi_rxf_intr, ssi_rxo_intr, ssi_rxu_intr, and ssi_mst_intr. |
Level |
187 |
SPI1 |
spi1_IRQ | This interrupt combines: ssi_txe_intr, ssi_txo_intr, ssi_rxf_intr, ssi_rxo_intr, ssi_rxu_intr, and ssi_mst_intr. |
Level |
188 |
SPI2 |
spi2_IRQ | This interrupt combines: ssi_txe_intr, ssi_txo_intr, ssi_rxf_intr, ssi_rxo_intr, ssi_rxu_intr, and ssi_mst_intr. |
Level |
189 |
SPI3 |
spi3_IRQ | This interrupt combines: ssi_txe_intr, ssi_txo_intr, ssi_rxf_intr, ssi_rxo_intr, ssi_rxu_intr, and ssi_mst_intr. |
Level |
190 |
I2C0 |
i2c0_IRQ | This interrupt combines: ic_rx_under_intr, ic_rx_full_intr, ic_tx_over_intr, ic_tx_empty_intr, ic_rd_req_intr, ic_tx_abrt_intr, ic_rx_done_intr, ic_activity_intr, ic_stop_det_intr, ic_start_det_intr, and ic_gen_call_intr. |
Level |
191 |
I2C1 |
i2c1_IRQ | This interrupt combines: ic_rx_under_intr, ic_rx_full_intr, ic_tx_over_intr, ic_tx_empty_intr, ic_rd_req_intr, ic_tx_abrt_intr, ic_rx_done_intr, ic_activity_intr, ic_stop_det_intr, ic_start_det_intr, and ic_gen_call_intr. |
Level |
192 |
I2C2 |
i2c2_IRQ | This interrupt combines: ic_rx_under_intr, ic_rx_full_intr, ic_tx_over_intr, ic_tx_empty_intr, ic_rd_req_intr, ic_tx_abrt_intr, ic_rx_done_intr, ic_activity_intr, ic_stop_det_intr, ic_start_det_intr, and ic_gen_call_intr. |
Level |
193 |
I2C3 |
i2c3_IRQ | This interrupt combines: ic_rx_under_intr, ic_rx_full_intr, ic_tx_over_intr, ic_tx_empty_intr, ic_rd_req_intr, ic_tx_abrt_intr, ic_rx_done_intr, ic_activity_intr, ic_stop_det_intr, ic_start_det_intr, and ic_gen_call_intr. |
Level |
194 |
UART0 |
uart0_IRQ | — |
Level |
195 |
UART1 |
uart1_IRQ | — |
Level |
196 |
GPIO0 |
gpio0_IRQ | — |
Level |
197 |
GPIO1 |
gpio1_IRQ | — |
Level |
198 |
GPIO2 |
gpio2_IRQ | — |
Level |
199 |
Timer0 |
timer_l4sp_0_IRQ | This interrupt combines: TIMINT1 and TIMINT2. |
Level |
200 |
Timer1 |
timer_l4sp_1_IRQ | This interrupt combines: TIMINT1 and TIMINT2. |
Level |
201 |
Timer2 |
timer_osc1_0_IRQ | This interrupt combines: TIMINT1 and TIMINT2. |
Level |
202 |
Timer3 |
timer_osc1_1_IRQ | This interrupt combines: TIMINT1 and TIMINT2. |
Level |
203 |
Watchdog0 |
wdog0_IRQ | — |
Level |
204 |
Watchdog1 |
wdog1_IRQ | — |
Level |
205 |
Clock manager |
clkmgr_IRQ | — |
Level |
206 |
Clock manager |
mpuwakeup_IRQ | — |
Level |
207 |
FPGA manager |
fpga_man_IRQ | This interrupt combines: fpga_man_irq[7] through fpga_man_irq[0]. |
Level |
208 |
CoreSight |
nCTIIRQ[0] | — |
Level |
209 |
CoreSight |
nCTIIRQ[1] | — |
Level |
210 |
On‑chip RAM |
ram_ecc_corrected_IRQ | — |
Level |
211 |
On‑chip RAM |
ram_ecc_uncorrected_IRQ | — |
Level |