High-speed Reed-Solomon IP Core User Guide

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ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

3.3.1. High-speed Reed-Solomon IP Core Signals

Table 12.  Clock and Reset Signals
Name Avalon-ST Type Direction Description
clk_clk clk Input The main system clock. The whole IP core operates on the rising edge of clk_clk .
reset_reset_n reset_n Input An active low signal that resets the entire system when asserted. You can assert this signal asynchronously. However, you must deassert it synchronous to the clk_clk signal. When the IP core recovers from reset, ensure that the data it receives is a complete packet.
Table 13.  Custom IP Core Avalon-ST Interface Signals
Name Avalon-ST Type Direction Description
in_ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the in_ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.
in_valid valid Input Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal.
in_data[] data Input Data input for each codeword, symbol by symbol. Valid only when you assert the in_valid signal. Width is P x M bits.

For the encoder, the number of information symbols (N - CHECK) is not necessarily a multiple of P. It means that the last input symbol may have to be filled with zeros.

out_data data Output Encoder output. In Qsys systems for the decoder, this Avalon-ST-compliant data bus includes all the Avalon-ST output data signals (out_error_out, out_decfail, out_symol_out),) with length log2(R+1) + 1.
out_decfail data Output Decoding failure.
out_errors_out error Output Number of error symbol that the IP core decides. Size is log2(R+1)
out_errorvalues_out error Output Error values.
out_ready ready Input Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal. If the source is unable to provide new data, it deasserts out_valid for one or more clock cycles until it is prepared to drive valid data interface signals.
out_symbols_out data Output Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered.
out_valid valid Output Data valid signal. The IP core asserts the out_valid signal high, whenever a valid output is on out_data ; the IP core deasserts the signal when there is no valid output on out_data .
Table 14.  Fractuarable IP Core Avalon-ST Interface Signals
Name Avalon-ST Type Direction Width Description
in-valid Valid Input 1 Master valid signal. If in_valid is low it sets all valid_ch_in to low.
in-data Data Input 320 symbols_in + 4 valid_ch_in + 2 mode_in + sync_in Data input.
valid_ch_in Part of in_data Input 4 Input valid signal for each channel.
symbols_in Part of in_data Input 32 Input symbols.
  • 100 GbE one channel
  • 50 GbE two channels
  • 25 GbE four channels
mode_in Part of in_data Input 2
  • 0: 1x100 GbE
  • 1: 2x50 GbE or 4x25GbE
  • 2: 4x25 GbE
sync_in Part of in_data Input 1 Synchronize the output channels.
out_valid Valid Output 1 Master valid signal. out_valid is valid if any valid_ch_out is valid, i.e. if valid_ch0 or valid_ch1 etc are valid.
out_data Data Output 320 decoded symbols + 4 valid_out + 2 mode_out + 4 sop_out + 4 eop_out +4 decfail+ 12 errors_out Output data.
errors_out Part of out_data Output 12 Number of error symbols that the IP core decides.
decfail Part of out_data Output 4 (Optional) decfail of each output channel
eop_out Part of out_data Output 4 (Optional) eop of each output channel
sop_out Part of out_data Output 4 (Optional) sop of each channels
mode_out Part of out_data Output 2 Output mode.
valid_ch_out Part of out_data Output 4 Valid signal for each channel
symbols_out Part of out_data Output 320 Output symbols:
  • 100 GbE one channel
  • 50 GbE two channels
  • 25 GbE four channels
Level Two Title