AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 8/05/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines 2. Board Design Guidelines for Stratix 10 SoC FPGAs 3. Interfacing to the FPGA for Stratix 10 SoC FPGAs 4. System Considerations for Stratix 10 SoC FPGAs 5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs 6. Recommended Resources for Stratix 10 SoC FPGAs
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines x
1.1. Introduction to the Stratix 10 SoC Device Design Guidelines Revision History
2. Board Design Guidelines for Stratix 10 SoC FPGAs x
2.1. Pin Connection Considerations for Board Design 2.2. HPS Clocking and Reset Design Considerations 2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 2.4. Design Guidelines for HPS Interfaces 2.5. HPS EMIF Design Considerations 2.6. HPS Memory Debug 2.7. Boundary Scan for HPS 2.8. Embedded Software Debugging and Trace 2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
2.1. Pin Connection Considerations for Board Design x
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1. Board-Related Intel® Quartus® Prime Settings x
2.1.1.1. Unused Pins
2.2. HPS Clocking and Reset Design Considerations x
2.2.1. HPS Clock Planning 2.2.2. Early Pin Planning and I/O Assignment Analysis 2.2.3. Pin Features and Connections for HPS Clocks, Reset and PoR 2.2.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 2.2.5. Internal Clocks 2.2.6. HPS Peripheral Reset Management
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory x
2.3.1. HPS Pin Multiplexing Design Considerations 2.3.2. HPS I/O Settings: Constraints and Drive Strengths
2.4. Design Guidelines for HPS Interfaces x
2.4.1. HPS EMAC PHY Interfaces 2.4.2. USB Interface Design Guidelines 2.4.3. SD/MMC and eMMC Card Interface Design Guidelines 2.4.4. Design Guidelines for Flash Interfaces 2.4.5. UART Interface Design Guidelines 2.4.6. I2C Interface Design Guidelines
2.4.1. HPS EMAC PHY Interfaces x
2.4.1.1. PHY Interfaces 2.4.1.2. PHY Interfaces Connected Through FPGA I/O 2.4.1.3. MDIO 2.4.1.4. Common PHY Interface Design Considerations
2.4.1.1. PHY Interfaces x
2.4.1.1.1. RMII 2.4.1.1.2. RGMII
2.4.1.2. PHY Interfaces Connected Through FPGA I/O x
2.4.1.2.1. GMII/MII 2.4.1.2.2. Adapting to RGMII 2.4.1.2.3. Adapting to RMII 2.4.1.2.4. Adapting to SGMII
2.4.1.4. Common PHY Interface Design Considerations x
2.4.1.4.1. Signal Integrity
2.4.4. Design Guidelines for Flash Interfaces x
2.4.4.1. NAND Flash Interface Design Guidelines
2.5. HPS EMIF Design Considerations x
2.5.1. Considerations for Connecting HPS to SDRAM 2.5.2. HPS SDRAM I/O Locations GUIDELINE: Intel® recommends that you use these automated default pin location assignments as a starting point. GUIDELINE: Verify the HPS memory controller I/O locations in the Intel® Quartus® Prime project pinout file in the “output_files” sub-folder before finalizing board layout. GUIDELINE: Make sure all I/O associated with the HPS memory interface are located within the active HPS EMIF I/O banks. Pin Assignments DQ/DQS Group Placement Unused HPS EMIF I/O Availability as FPGA GPIO
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs x
3.1. Overview of HPS Memory-Mapped Interfaces 3.2. Recommended System Topologies 3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.4. Timing Closure for FPGA Accelerators 3.5. Information on How to Configure and Use the Bridges 3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces x
3.1.1. HPS-to-FPGA Bridge 3.1.2. Lightweight HPS-to-FPGA Bridge 3.1.3. FPGA-to-HPS Bridge 3.1.4. FPGA-to-SDRAM Ports 3.1.5. Interface Bandwidths
3.2. Recommended System Topologies x
3.2.1. HPS Accesses to FPGA Fabric 3.2.2. MPU Sharing Data with FPGA 3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA x
3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 3.2.3.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 3.2.3.3. Example 3: FPGA Reading Cache Coherent Data from HPS 3.2.3.4. Example 4: FPGA Writing Cache Coherent Data to HPS
4. System Considerations for Stratix 10 SoC FPGAs x
4.1. Timing Considerations 4.2. Maximizing Performance 4.3. System Level Cache Coherency 4.4. System Considerations for Stratix 10 SoC FPGAs Revision History
4.1. Timing Considerations x
4.1.1. Timing Closure for FPGA Accelerators 4.1.2. USB Interface Design Guidelines
4.1.1. Timing Closure for FPGA Accelerators x
4.1.1.1. HPS First and FPGA First Boot Considerations
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs x
5.1. Overview 5.2. Assembling the Components of Your Software Development Platform 5.3. Golden Hardware Reference Design (GHRD) 5.4. Selecting an Operating System for Your Application 5.5. Assembling Your Software Development Platform for Linux* 5.6. Assembling your Software Development Platform for a Bare-Metal Application 5.7. Assembling your Software Development Platform for Partner OS or RTOS 5.8. Choosing the Bootloader Software 5.9. Selecting Software Tools for Development, Debug and Trace 5.10. Boot And Configuration Considerations 5.11. System Reset Considerations 5.12. Flash Considerations 5.13. Embedded Software Debugging and Trace 5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
5.4. Selecting an Operating System for Your Application x
5.4.1. Using Linux* or RTOS 5.4.2. Developing a Bare-Metal Application 5.4.3. Using the Bootloader as a Bare-Metal Framework 5.4.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.5. Assembling Your Software Development Platform for Linux* x
5.5.1. Golden System Reference Design (GSRD) for Linux* 5.5.2. Source Code Management Considerations
5.9. Selecting Software Tools for Development, Debug and Trace x
5.9.1. Selecting Software Build Tools 5.9.2. Selecting Software Debug Tools 5.9.3. Selecting Software Trace Tools
5.10. Boot And Configuration Considerations x
5.10.1. Configuration Sources 5.10.2. Configuration Flash 5.10.3. Configuration Clock 5.10.4. Selecting HPS Boot Options 5.10.5. HPS Boot Sources 5.10.6. Remote System Update (RSU)
5.12. Flash Considerations x
5.12.1. Flash Programming Method 5.12.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
6. Recommended Resources for Stratix 10 SoC FPGAs x
6.1. Device Documentation 6.2. Tools and Software Web Pages 6.3. Recommended Resources for Intel® Stratix® 10 SoC FPGAs Revision History
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs

2.5.2. HPS SDRAM I/O Locations

The Intel® Agilex™ EMIF for HPS IP includes default pin location assignments for all the external memory interface signals in constraint files created at IP generation time and read by Intel® Quartus® Prime Pro Edition software during design compilation.

GUIDELINE: Intel® recommends that you use these automated default pin location assignments as a starting point.

You may need to modify the default pinout to meet the restrictions shown in this section.

GUIDELINE: Verify the HPS memory controller I/O locations in the Intel® Quartus® Prime project pinout file in the “output_files” sub-folder before finalizing board layout.

By default, Intel® Quartus® Prime generates output reports, log files and programming files in the “output_files” subfolder of the project folder. See the .pin text file after compilation for the pinout for your design, including the pin locations for the HPS EMIF.

GUIDELINE: Make sure all I/O associated with the HPS memory interface are located within the active HPS EMIF I/O banks.

It is critical that you ensure all I/O necessary for a functioning HPS memory interface are located within the active banks for your HPS memory width as shown in the table below:
Table 9.  HPS SDRAM I/O Locations
EMIF Width Bank 2N Lanes Bank 2M Lanes Bank 2L Lanes
3 2 1 0 3 2 1 0 3 2 1 0
16-bit GPIO 16-bit Data NC4 Address/Command/RZQ/RefClk GPIO
16-bit + ECC GPIO 16-bit Data + ECC Address/Command/RZQ/RefClk GPIO
32-bit 32-bit Data NC Address/Command/RZQ/RefClk GPIO
32-bit + ECC 32-bit Data + ECC Address/Command/RZQ/RefClk GPIO
64-bit 64-bit Data NC Address/Command/RZQ/RefClk 64-bit Data
64-bit + ECC 64-bit Data + ECC Address/Command/RZQ/RefClk 64-bit Data + ECC

Pin Assignments

Within a single data lane (which implements a single x8 DQS group):
  • DQ pins must use pins at indices: 1, 2, 3, 6, 7, 8, 9, 10. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
  • DM/DBI pin must use pin at index 11. There is no flexibility.
  • DQS must use pin at index 4, and DQS# must use pin at index 5. There is no flexibility.
  • Place ALERT# pin in I/O bank 2N, Lane 0, pin index 0 or I/O bank 2N, Lane 1, pin index 0. Otherwise, pin index 0 must have "no connect"; unless it is used for HPS REFCLK_P, Address/Command/RZQ/RefClk, or general-purpose I/O, where allowed.
  • Assignment of data lanes must be as illustrated in the above table. You can swap the locations of entire byte lanes (that is, you may swap locations of byte 0 and byte 1) so long as the resulting pin-out uses only the lanes permitted by your HPS EMIF configuration, as shown in the above table.
  • I/O bank 2M Lane 0, 1, and 2 must only be used for Address/Command/RZQ/RefClk, otherwise “no connect”.
  • You must not change placement of the address and command pins from the default.
  • If not using ECC, IO bank 2M Lane 3 must be “no connect”. If using ECC, the ECC DQS group can be in any single data lane that is not otherwise restricted, that is, there is no requirement for the ECC DQS group to be placed in 2M.
  • HPS REFCLK_P must use IO bank 2M Lane 2 pin index 0. HPS REFCLK_N must use IO bank 2M Lane 2 pin index 1.
  • RZQ must use IO bank 2M Lane 2 pin index 2.

DQ/DQS Group Placement

Configuration DQS Group Placement
16 bit Must be placed in I/O lanes 0 and 1 of 2N.
16 bit + ECC Must be placed in I/O lanes 0 and 1 of 2N and I/O lane 3 of 2M.
32 bit Must be placed in 2N.
32 bit + ECC Must be placed in 2N and I/O lane 3 of 2M.
64 bit Must be placed in 2N and 2L.
64 bit + ECC Must be placed in 2N, 2L, and I/O lane 3 of 2M.
Note: In all cases, the DQ/DQS groups can be swapped around in the I/O banks shown. There is no requirement for the ECC DQS group to be placed in 2M.

Unused HPS EMIF I/O Availability as FPGA GPIO

  • Bank 2N (Data[31:0])—Unused lanes for 16-bit interfaces are available for FPGA GPIO.
  • Band 2M (Addr/Cmd/ECC)
    • Lanes 0, 1, 2 are NOT AVAILABLE as FPGA GPIO
    • Lane 3 is NOT AVAILABLE as FPGA GPIO when not using ECC
  • Bank 2L (Data[63:32])—Unused lanes for 32-bit or less interfaces are available as FPGA GPIO
4 NC indicates "no connect".
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