AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 8/05/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines 2. Board Design Guidelines for Stratix 10 SoC FPGAs 3. Interfacing to the FPGA for Stratix 10 SoC FPGAs 4. System Considerations for Stratix 10 SoC FPGAs 5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs 6. Recommended Resources for Stratix 10 SoC FPGAs
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines x
1.1. Introduction to the Stratix 10 SoC Device Design Guidelines Revision History
2. Board Design Guidelines for Stratix 10 SoC FPGAs x
2.1. Pin Connection Considerations for Board Design 2.2. HPS Clocking and Reset Design Considerations 2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 2.4. Design Guidelines for HPS Interfaces 2.5. HPS EMIF Design Considerations 2.6. HPS Memory Debug 2.7. Boundary Scan for HPS 2.8. Embedded Software Debugging and Trace 2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
2.1. Pin Connection Considerations for Board Design x
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1. Board-Related Intel® Quartus® Prime Settings x
2.1.1.1. Unused Pins
2.2. HPS Clocking and Reset Design Considerations x
2.2.1. HPS Clock Planning 2.2.2. Early Pin Planning and I/O Assignment Analysis 2.2.3. Pin Features and Connections for HPS Clocks, Reset and PoR 2.2.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 2.2.5. Internal Clocks 2.2.6. HPS Peripheral Reset Management
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory x
2.3.1. HPS Pin Multiplexing Design Considerations 2.3.2. HPS I/O Settings: Constraints and Drive Strengths
2.4. Design Guidelines for HPS Interfaces x
2.4.1. HPS EMAC PHY Interfaces GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability. GUIDELINE: A GMII-to-SGMII adapter is available to automatically adapt to transceiver-based SGMII optical modules. 2.4.2. USB Interface Design Guidelines 2.4.3. SD/MMC and eMMC Card Interface Design Guidelines 2.4.4. Design Guidelines for Flash Interfaces 2.4.5. UART Interface Design Guidelines 2.4.6. I2C Interface Design Guidelines
2.4.1. HPS EMAC PHY Interfaces x
GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability. GUIDELINE: A GMII-to-SGMII adapter is available to automatically adapt to transceiver-based SGMII optical modules. 2.4.1.1. PHY Interfaces 2.4.1.2. PHY Interfaces Connected Through FPGA I/O 2.4.1.3. MDIO 2.4.1.4. Common PHY Interface Design Considerations
2.4.1.1. PHY Interfaces x
2.4.1.1.1. RMII 2.4.1.1.2. RGMII
2.4.1.2. PHY Interfaces Connected Through FPGA I/O x
2.4.1.2.1. GMII/MII 2.4.1.2.2. Adapting to RGMII 2.4.1.2.3. Adapting to RMII 2.4.1.2.4. Adapting to SGMII
2.4.1.4. Common PHY Interface Design Considerations x
2.4.1.4.1. Signal Integrity
2.4.4. Design Guidelines for Flash Interfaces x
2.4.4.1. NAND Flash Interface Design Guidelines
2.5. HPS EMIF Design Considerations x
2.5.1. Considerations for Connecting HPS to SDRAM 2.5.2. HPS SDRAM I/O Locations
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs x
3.1. Overview of HPS Memory-Mapped Interfaces 3.2. Recommended System Topologies 3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.4. Timing Closure for FPGA Accelerators 3.5. Information on How to Configure and Use the Bridges 3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces x
3.1.1. HPS-to-FPGA Bridge 3.1.2. Lightweight HPS-to-FPGA Bridge 3.1.3. FPGA-to-HPS Bridge 3.1.4. FPGA-to-SDRAM Ports 3.1.5. Interface Bandwidths
3.2. Recommended System Topologies x
3.2.1. HPS Accesses to FPGA Fabric 3.2.2. MPU Sharing Data with FPGA 3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA x
3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 3.2.3.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 3.2.3.3. Example 3: FPGA Reading Cache Coherent Data from HPS 3.2.3.4. Example 4: FPGA Writing Cache Coherent Data to HPS
4. System Considerations for Stratix 10 SoC FPGAs x
4.1. Timing Considerations 4.2. Maximizing Performance 4.3. System Level Cache Coherency 4.4. System Considerations for Stratix 10 SoC FPGAs Revision History
4.1. Timing Considerations x
4.1.1. Timing Closure for FPGA Accelerators 4.1.2. USB Interface Design Guidelines
4.1.1. Timing Closure for FPGA Accelerators x
4.1.1.1. HPS First and FPGA First Boot Considerations
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs x
5.1. Overview 5.2. Assembling the Components of Your Software Development Platform 5.3. Golden Hardware Reference Design (GHRD) 5.4. Selecting an Operating System for Your Application 5.5. Assembling Your Software Development Platform for Linux* 5.6. Assembling your Software Development Platform for a Bare-Metal Application 5.7. Assembling your Software Development Platform for Partner OS or RTOS 5.8. Choosing the Bootloader Software 5.9. Selecting Software Tools for Development, Debug and Trace 5.10. Boot And Configuration Considerations 5.11. System Reset Considerations 5.12. Flash Considerations 5.13. Embedded Software Debugging and Trace 5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
5.4. Selecting an Operating System for Your Application x
5.4.1. Using Linux* or RTOS 5.4.2. Developing a Bare-Metal Application 5.4.3. Using the Bootloader as a Bare-Metal Framework 5.4.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.5. Assembling Your Software Development Platform for Linux* x
5.5.1. Golden System Reference Design (GSRD) for Linux* 5.5.2. Source Code Management Considerations
5.9. Selecting Software Tools for Development, Debug and Trace x
5.9.1. Selecting Software Build Tools 5.9.2. Selecting Software Debug Tools 5.9.3. Selecting Software Trace Tools
5.10. Boot And Configuration Considerations x
5.10.1. Configuration Sources 5.10.2. Configuration Flash 5.10.3. Configuration Clock 5.10.4. Selecting HPS Boot Options 5.10.5. HPS Boot Sources 5.10.6. Remote System Update (RSU)
5.12. Flash Considerations x
5.12.1. Flash Programming Method 5.12.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
6. Recommended Resources for Stratix 10 SoC FPGAs x
6.1. Device Documentation 6.2. Tools and Software Web Pages 6.3. Recommended Resources for Intel® Stratix® 10 SoC FPGAs Revision History
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs

2.4.1. HPS EMAC PHY Interfaces

There are three EMACs based on the Synopsys* DesignWare* 3504‑0 Universal 10/100/1000 Ethernet MAC IP version. When configuring an HPS component for EMAC peripherals within Platform Designer, you must select from one of the following supported PHY interfaces, located in the HPS Dedicated I/O Bank2, for each EMAC instance:
  • Reduced Media Independent Interface (RMII)
  • Reduced Gigabit Media Independent Interface (RGMII)
Note: RGMII- Internal Delay (RGMII-ID) is a component of the RGMII version 2.0 specification that defines the capability of a transmitter to add delay on the forwarded data path clock to center that clock in the data. It adds delay on both: TX_CLK at the transmitter (MAC) and RX_CLK at the transmitter (PHY). Pin muxes in the HPS Dedicated I/O Bank feature the ability to add up to 2.4ns of delay in increments of 150ps, which is more than the required 1.5ns to center the clock in the transmit data at the PHY.

GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability.

The Intel® Stratix® 10 SoC Development Kit uses the Microchip KSZ9031 Ethernet PHY. This device is known to work with the Intel® Stratix® 10 HPS Ethernet PHY interface and software device drivers.

It is possible to adapt the MII/GMII PHY interfaces exposed to the FPGA fabric by the HPS component to other PHY interface standards such as RMII, SGMII, SMII and TBI using soft adaptation logic in the FPGA and features in the general-purpose FPGA I/O and transceiver FPGA I/O.

For more information, refer to the device drivers available for your operating system of choice or the Linux device driver provided with the Intel® Stratix® 10 SoC development kit.

The EMAC provides a variety of PHY interfaces and control options through the HPS and the FPGA I/Os.

For designs that are pin-limited on HPS I/O, the EMAC can be configured to expose either a GMII or MII PHY interface to the FPGA fabric, which can be routed directly to FPGA I/O pins. Exposing the PHY interface to the FPGA fabric also allows adapting the GMII/MII to other PHY interface types such as SGMII and RMII using soft logic with the appropriate general purpose or transceiver I/O resources.
Note: You can connect PHYs to the HPS EMACs through the FPGA fabric using the GMII and MII bus interfaces for Gigabit and 10/100 Mbps access respectively.

GUIDELINE: A GMII-to-SGMII adapter is available to automatically adapt to transceiver-based SGMII optical modules.

The EMAC also provides the I2C instead of the MDIO for their control interface. The HPS or FPGA can use three of the five general purpose I2C peripherals for controlling the PHY devices:
  • i2c_emac_0
  • i2c_emac_1
  • i2c_emac_2

Section Content
PHY Interfaces
PHY Interfaces Connected Through FPGA I/O
MDIO
Common PHY Interface Design Considerations

Related Information
2 The HPS Dedicated I/O Bank consists of 48 I/O with 1.8V signaling.
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