AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

Download PDF
ID 683117
Date 8/05/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines 2. Board Design Guidelines for Stratix 10 SoC FPGAs 3. Interfacing to the FPGA for Stratix 10 SoC FPGAs 4. System Considerations for Stratix 10 SoC FPGAs 5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs 6. Recommended Resources for Stratix 10 SoC FPGAs
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines x
1.1. Introduction to the Stratix 10 SoC Device Design Guidelines Revision History
2. Board Design Guidelines for Stratix 10 SoC FPGAs x
2.1. Pin Connection Considerations for Board Design 2.2. HPS Clocking and Reset Design Considerations 2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 2.4. Design Guidelines for HPS Interfaces 2.5. HPS EMIF Design Considerations 2.6. HPS Memory Debug 2.7. Boundary Scan for HPS 2.8. Embedded Software Debugging and Trace 2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
2.1. Pin Connection Considerations for Board Design x
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1. Board-Related Intel® Quartus® Prime Settings x
2.1.1.1. Unused Pins
2.2. HPS Clocking and Reset Design Considerations x
2.2.1. HPS Clock Planning 2.2.2. Early Pin Planning and I/O Assignment Analysis 2.2.3. Pin Features and Connections for HPS Clocks, Reset and PoR 2.2.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 2.2.5. Internal Clocks 2.2.6. HPS Peripheral Reset Management
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory x
2.3.1. HPS Pin Multiplexing Design Considerations 2.3.2. HPS I/O Settings: Constraints and Drive Strengths
2.4. Design Guidelines for HPS Interfaces x
2.4.1. HPS EMAC PHY Interfaces 2.4.2. USB Interface Design Guidelines 2.4.3. SD/MMC and eMMC Card Interface Design Guidelines 2.4.4. Design Guidelines for Flash Interfaces 2.4.5. UART Interface Design Guidelines 2.4.6. I2C Interface Design Guidelines
2.4.1. HPS EMAC PHY Interfaces x
2.4.1.1. PHY Interfaces 2.4.1.2. PHY Interfaces Connected Through FPGA I/O 2.4.1.3. MDIO 2.4.1.4. Common PHY Interface Design Considerations
2.4.1.1. PHY Interfaces x
2.4.1.1.1. RMII 2.4.1.1.2. RGMII I/O Pin Timing Transmit path setup/hold GUIDELINE: For TX_CLK from the Stratix 10, you must introduce 1.8 ns I/O delay to meet the 1.0 ns PHY minimum input setup/hold time in the RGMII spec. GUIDELINE: Ensure your design includes the necessary Intel settings to configure the HPS EMAC outputs for the required delays. Receive path setup/hold GUIDELINE: If the PHY does not support RGMII-ID, use the configurable delay elements in the Stratix 10 SoC HPS dedicated I/O or FPGA I/O to center the RX_CLK in the center of the RX_DATA/CTL data valid window.
2.4.1.2. PHY Interfaces Connected Through FPGA I/O x
2.4.1.2.1. GMII/MII 2.4.1.2.2. Adapting to RGMII 2.4.1.2.3. Adapting to RMII 2.4.1.2.4. Adapting to SGMII
2.4.1.4. Common PHY Interface Design Considerations x
2.4.1.4.1. Signal Integrity
2.4.4. Design Guidelines for Flash Interfaces x
2.4.4.1. NAND Flash Interface Design Guidelines
2.5. HPS EMIF Design Considerations x
2.5.1. Considerations for Connecting HPS to SDRAM 2.5.2. HPS SDRAM I/O Locations
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs x
3.1. Overview of HPS Memory-Mapped Interfaces 3.2. Recommended System Topologies 3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.4. Timing Closure for FPGA Accelerators 3.5. Information on How to Configure and Use the Bridges 3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces x
3.1.1. HPS-to-FPGA Bridge 3.1.2. Lightweight HPS-to-FPGA Bridge 3.1.3. FPGA-to-HPS Bridge 3.1.4. FPGA-to-SDRAM Ports 3.1.5. Interface Bandwidths
3.2. Recommended System Topologies x
3.2.1. HPS Accesses to FPGA Fabric 3.2.2. MPU Sharing Data with FPGA 3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA x
3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 3.2.3.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 3.2.3.3. Example 3: FPGA Reading Cache Coherent Data from HPS 3.2.3.4. Example 4: FPGA Writing Cache Coherent Data to HPS
4. System Considerations for Stratix 10 SoC FPGAs x
4.1. Timing Considerations 4.2. Maximizing Performance 4.3. System Level Cache Coherency 4.4. System Considerations for Stratix 10 SoC FPGAs Revision History
4.1. Timing Considerations x
4.1.1. Timing Closure for FPGA Accelerators 4.1.2. USB Interface Design Guidelines
4.1.1. Timing Closure for FPGA Accelerators x
4.1.1.1. HPS First and FPGA First Boot Considerations
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs x
5.1. Overview 5.2. Assembling the Components of Your Software Development Platform 5.3. Golden Hardware Reference Design (GHRD) 5.4. Selecting an Operating System for Your Application 5.5. Assembling Your Software Development Platform for Linux* 5.6. Assembling your Software Development Platform for a Bare-Metal Application 5.7. Assembling your Software Development Platform for Partner OS or RTOS 5.8. Choosing the Bootloader Software 5.9. Selecting Software Tools for Development, Debug and Trace 5.10. Boot And Configuration Considerations 5.11. System Reset Considerations 5.12. Flash Considerations 5.13. Embedded Software Debugging and Trace 5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
5.4. Selecting an Operating System for Your Application x
5.4.1. Using Linux* or RTOS 5.4.2. Developing a Bare-Metal Application 5.4.3. Using the Bootloader as a Bare-Metal Framework 5.4.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.5. Assembling Your Software Development Platform for Linux* x
5.5.1. Golden System Reference Design (GSRD) for Linux* 5.5.2. Source Code Management Considerations
5.9. Selecting Software Tools for Development, Debug and Trace x
5.9.1. Selecting Software Build Tools 5.9.2. Selecting Software Debug Tools 5.9.3. Selecting Software Trace Tools
5.10. Boot And Configuration Considerations x
5.10.1. Configuration Sources 5.10.2. Configuration Flash 5.10.3. Configuration Clock 5.10.4. Selecting HPS Boot Options 5.10.5. HPS Boot Sources 5.10.6. Remote System Update (RSU)
5.12. Flash Considerations x
5.12.1. Flash Programming Method 5.12.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
6. Recommended Resources for Stratix 10 SoC FPGAs x
6.1. Device Documentation 6.2. Tools and Software Web Pages 6.3. Recommended Resources for Intel® Stratix® 10 SoC FPGAs Revision History
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs

2.4.1.1.2. RGMII

RGMII is the most common interface because it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer.

RGMII uses four-bit wide transmit and receive data paths, each with its own source-synchronous clock. All transmit data and control signals are source synchronous to TX_CLK, and all receive data and control signals are source synchronous to RX_CLK.

For all speed modes, TX_CLK is sourced by the MAC, and RX_CLK is sourced by the PHY. In 1000 Mbps mode, TX_CLK and RX_CLK are 125 MHz, and Dual Data Rate (DDR) signaling is used. In 10 Mbps and 100 Mbps modes, TX_CLK and RX_CLK are 2.5 MHz and 25 MHz, respectively, and rising edge Single Data Rate (SDR) signaling is used.

Figure 4. RGMII MAC/PHY Interface

I/O Pin Timing

This section addresses RGMII interface timing from the perspective of meeting requirements in the 1000 Mbps mode. The interface timing margins are most demanding in 1000 Mbps mode, thus it is the only scenario you consider here.

At 125 MHz, the period is 8 ns, but because both edges are used, the effective period is only 4 ns. The TX and RX busses are separate and source synchronous, simplifying timing. The RGMII specification calls for CLK to be delayed from DATA at the receiver in either direction by a minimum 1.0 ns and a maximum 2.6 ns.

In other words, the TX_CLK must be delayed from the MAC output to the PHY input and the RX_CLK from the PHY output to the MAC input. The signals are transmitted source synchronously within the +/- 500 ps RGMII skew specification in each direction as measured at the output pins. The minimum delay needed in each direction is 1 ns but Intel® recommends to target a delay of 1.5 ns to 2.0 ns to ensure significant timing margin.

Transmit path setup/hold

Only setup and hold for TX_CLK to TX_CTL and TXD[3:0] matter for transmit. The Intel® Stratix® 10 I/O can provide up to 2.4 ns additional delay on outputs in 150 ps increments. This delay is enabled using the output delay logic option within the assignment editor in Intel® Quartus® Prime.

GUIDELINE: For TX_CLK from the Stratix 10, you must introduce 1.8 ns I/O delay to meet the 1.0 ns PHY minimum input setup/hold time in the RGMII spec.

The Intel® Stratix® 10 SoC HPS dedicated I/O and FPGA I/O support adding up to 2.4 ns of output delay in 150 ps increments. The delay added to the MAC's TX_CLK output when using HPS dedicated I/O can be configured in the HPS Platform Designer IP component.

GUIDELINE: Ensure your design includes the necessary Intel settings to configure the HPS EMAC outputs for the required delays.

On the Intel® Stratix® 10 SoC Development Kit and the associated Intel® Stratix® 10 Golden Hardware Reference Design (the GHRD is the hardware component of the GSRD), an example for setting the output delay setting on TX_CLK can be found in the HPS Platform Designer IP component configuration.

Receive path setup/hold

Only setup and hold for RX_CLK to RX_CTL and RXD[3:0] are necessary to consider for receive timings. The Intel® Stratix® 10 I/O can provide up to 3200 ps additional delay on inputs. For Intel® Stratix® 10 inputs, the 3.2 ns I/O delay can achieve this timing for RX_CLK without any other considerations on the PHY side or board trace delay side.

GUIDELINE: If the PHY does not support RGMII-ID, use the configurable delay elements in the Stratix 10 SoC HPS dedicated I/O or FPGA I/O to center the RX_CLK in the center of the RX_DATA/CTL data valid window.

If using HPS I/O, configure delay on the RX_CLK in the HPS Platform Designer IP component. If using FPGA I/O, add delay on the RX_CLK input with an input delay setting in the project settings file (.qsf).

Level Two Title