40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

2.8. Simulating the 40‑100GbE IP Core With the Testbenches

You can simulate the 40‑100GbE IP core using the Altera-supported versions of the Mentor Graphics ModelSim® SE, Cadence NCSim, and Synopsys VCS simulators for the current version of the Quartus Prime software. The simulator does not have the capacity to simulate this IP core.

The example testbenches simulate packet traffic at the digital level. The testbenches do not require special SystemVerilog class libraries.

The top-level testbench file for non-40GBASE-KR4 variations consists of a simple packet generator and checker and one IP core in a loopback configuration. The packet generator skews and reorders its transmitter digital output to emulate actual transceiver behavior and optical cabling lane permutations.

The top-level testbench file for 40GBASE-KR4 variations consists of a symmetric arrangement with two IP cores and traffic between them. For each IP core there is a packet generator to send traffic on the TX side of the IP core and a packet checker to check the packets it receives from the other IP core. The two IP cores communicate with each other through their Ethernet link, in which the testbench injects random skew. The 40GBASE-KR4 testbench connects each IP core to a reconfiguration bundle , and exercises auto-negotiation, link training, and data mode.

The example testbenches contain the test files and run scripts for the ModelSim, Cadence, and Synopsys simulators. The run scripts use the file lists in the wrapper files. When you launch a simulation from the original directory, the relative filenames in the wrapper files allow the run script to locate the files correctly. You can access design files from any location if your directory structure matches the structure assumed in the run script path names.

The following examples provide directions for generating the testbench and running tests with the ModelSim, Cadence, and Synopsys simulators.