JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683113
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.10. Software Control Flow

Note: The software control flow is only supported by the Nios Control design example.

The key feature of the Nios Control design example is the ability to control the behavior of the JESD204B system using a C-based, software control flow.

The software control flow allows you to perform the following tasks:

  • System reset—ability to reset individual modules (core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.
  • Initial and dynamic, real-time configuration of external converter devices via SPI interface.
  • Dynamic reconfiguration of key modules in the design example subsystem (for example, JESD204B IP core base layer, transceiver PHY, core PLL).
  • Error handling via interrupt service routines (ISR).
  • Status register readback.
  • Dynamic switching between real-time operation and test mode.

The software C code included as part of the design example only performs basic JESD204B link initialization. You can modify the code to perform some or all of the tasks above as per your system specifications. The software C code (main.c) executes a sequence of tasks as shown in the figure below.

Note: The software C code assumes that the Nios Control design is configured in duplex mode. Make your own modifications if using simplex mode design.
Figure 17. Software C Code Task Sequence

The JESD204B link initialization sequence accomplishes the following tasks:

  • Set the pattern type for the pattern generator and checker. The default pattern type is set to PRBS.
  • Set the loopback mode. The default is internal serial loopback mode.
  • Pulse SYSREF (required to meet Subclass 1 requirements)
  • Wait 10 seconds to allow for changes to take effect.
  • Report the link status.

Section Content
Software Parameters
Interrupt Service Routines (ISR)
Software Functions Description

Level Two Title