JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
ID
683113
Date
10/14/2022
Public
Visible to Intel only — GUID: yxs1488878494495
Ixiasoft
1.2.10.3. Software Functions Description
The software C code generated with the design example performs basic JESD204B link initialization and exits. This section describes the functions used in the main.c code and also the macros library that facilitates access to the configuration and status registers (CSR) of the JESD204B design example system. These functions and macros provide the building blocks for you to customize the software code to your system specifications.