JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.10.2. Interrupt Service Routines (ISR)

One key feature of the Nios Control design example is the ability to handle interrupt requests (IRQ) from peripherals through the software interrupt service routines (ISR).

In this design example, the following peripherals have their IRQ output ports connected to the IRQ input port of the Nios processor:

  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • SPI master
  • Timer
  • Reset sequencer

The software C code included as part of the design example defines the ISRs for the following peripherals:

  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • SPI master

The ISRs in the C code is a basic routine that performs two tasks:

  • Clear IRQ error flag
  • Print error type and message (for JESD204B IP core TX and RX base layer ISR only)

Error types and messages printed by the JESD204B IP core TX base layer ISR:

  • SYNC_N error
  • SYSREF LMFC error
  • DLL data invalid error
  • Transport layer data invalid error
  • SYNC_N link reinitialization request
  • Transceiver PLL locked error
  • Phase compensation FIFO full error
  • Phase compensation FIFO empty error
  • Error types and messages printed by the JESD204B IP core RX base layer ISR:
  • SYSREF LMFC error
  • DLL data ready error
  • Transport layer data ready error
  • Lane deskew error
  • RX locked to data error
  • Phase compensation FIFO full error
  • Phase compensation FIFO empty error
  • Code group synchronization error
  • Frame alignment error
  • Lane alignment error
  • Unexpected K character
  • Not in table error
  • Running disparity error
  • Initial Lane Alignment Sequence (ILAS) error
  • DLL error reserve status
  • ECC error corrected
  • ECC error fatal

The error types correspond to the tx_err, rx_err0, and rx_err1 status registers in the JESD204B IP core TX and RX register maps respectively. Refer to the JESD204B RX Address Map and Register Definitions and JESD204B TX Address Map and Register Definitions for more details on the TX and RX error registers. The PRINT_INTERRUPT_MESSAGES parameter in the main.h header file controls the printing of interrupt error messages to the standard output. Set the parameter to 1 (default) to print error messages, else set to 0. Refer to Software Parameters for more details. You can modify the ISRs in the C code to customize the interrupt handling response based on your system specifications.

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