JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.10.1. Software Parameters

The software parameters defined in the main header file (main.h) control various behaviors of the C code.

Table 21.  Software Parameters
Parameter Default Value Description
DEBUG_MODE 0 Set to 1 to print debug messages, else set to 0.
PRINT_INTERRUPT_MESSAGES 1 Set to 1 to print JESD204B error interrupt messages, else set to 0.
PATCHK_EN 1 Set to 1 when test pattern checker is included in the initial design data path configuration, else set to 0.
DATAPATH 3

Set to indicate the JESD204B IP configuration:

1 – TX data path only.

2 – RX data path only.

3 – Duplex data path (TX and RX data path).
MAX_LINKS 1

Set to indicate the number of links in the design (for example, for dual link, set MAX_LINKS=2). See Implementing a Multi-Link Design section for more detailed instructions on implementing multi-link use case.

Note: When using the design as-is, the maximum value of MAX_LINKS is 16. To increase the limit, redesign the address map in Platform Designer.
LOOPBACK_INIT 1 Initial value of the loopback. Set to 1 for internal serial loopback mode, else set to 0.
SOURCEDEST_INIT PRBS

Initial value of source/destination. Set to indicate test pattern generator or checker type or user mode:

USER – User mode (no test pattern generator or checker in data path).

ALT – Test pattern generator or checker set in alternate checkerboard mode.

RAMP – Test pattern generator or checker set in ramp wave mode.

PRBS – Test pattern generator or checker set in parallel PRBS mode.

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