L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

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ID 683111
Date 9/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Interrupts 8. Registers 9. Testbench and Design Example 10. Document Revision History A. PCI Express Core Architecture B. TX Credit Adjustment Sample Code C. Root Port Enumeration D. Troubleshooting and Observing the Link Status
1. Introduction x
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-ST RX Interface 3.2. Avalon-ST TX Interface 3.3. TX Credit Interface 3.4. TX and RX Serial Data 3.5. Clocks 3.6. Function-Level Reset (FLR) Interface 3.7. Control Shadow Interface for SR-IOV 3.8. Configuration Extension Bus Interface 3.9. Hard IP Reconfiguration Interface 3.10. Interrupt Interfaces 3.11. Power Management Interface 3.12. Reset 3.13. Transaction Layer Configuration Interface 3.14. PLL Reconfiguration Interface 3.15. PIPE Interface (Simulation Only)
4. Parameters x
4.1. Stratix 10 Avalon-ST Settings 4.2. Multifunction and SR-IOV System Settings 4.3. Base Address Registers 4.4. Device Identification Registers 4.5. TPH/ATS Capabilities 4.6. PCI Express and PCI Capabilities Parameters 4.7. Configuration, Debug and Extension Options 4.8. PHY Characteristics 4.9. Example Designs
4.6. PCI Express and PCI Capabilities Parameters x
4.6.1. Device Capabilities 4.6.2. Link Capabilities 4.6.3. MSI and MSI-X Capabilities 4.6.4. Slot Capabilities 4.6.5. Power Management 4.6.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 5.4. Integration and Implementation 5.5. Required Supporting IP Cores 5.6. Channel Layout and PLL Usage
5.2. Simulation x
5.2.1. Selecting Serial or PIPE Simulation
5.4. Integration and Implementation x
5.4.1. Clock Requirements 5.4.2. Reset Requirements
5.5. Required Supporting IP Cores x
5.5.1. Hard Reset Controller 5.5.2. TX PLL
6. Block Descriptions x
6.1. Interfaces 6.2. Errors reported by the Application Layer 6.3. Power Management 6.4. Transaction Ordering 6.5. RX Buffer
6.1. Interfaces x
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 6.1.2. Avalon-ST 256-Bit RX Interface 6.1.3. Avalon-ST 512-Bit RX Interface 6.1.4. Avalon-ST 256-Bit TX Interface 6.1.5. Avalon-ST 512-Bit TX Interface 6.1.6. TX Credit Interface 6.1.7. Interpreting the TX Credit Interface 6.1.8. Clocks 6.1.9. Update Flow Control Timer and Credit Release 6.1.10. Function-Level Reset (FLR) Interface 6.1.11. Resets 6.1.12. Interrupts 6.1.13. Control Shadow Interface for SR-IOV 6.1.14. Transaction Layer Configuration Space Interface 6.1.15. Configuration Extension Bus Interface 6.1.16. Hard IP Status Interface 6.1.17. Hard IP Reconfiguration 6.1.18. Power Management Interface 6.1.19. Serial Data Interface 6.1.20. PIPE Interface 6.1.21. Test Interface 6.1.22. PLL IP Reconfiguration 6.1.23. Message Handling
6.1.2. Avalon-ST 256-Bit RX Interface x
6.1.2.1. Avalon-ST RX Interface Three- and Four-Dword TLPs 6.1.2.2. Avalon-ST RX Interface rx_st_ready Deasserts for the 256-Bit Interface 6.1.2.3. Avalon-ST RX Interface rx_st_valid Deasserts 6.1.2.4. Avalon-ST RX Back-to-Back Transmission 6.1.2.5. Avalon-ST RX Interface Single-Cycle TLPs
6.1.3. Avalon-ST 512-Bit RX Interface x
6.1.3.1. PCIe TLP Layout Using the 512-Bit Interface
6.1.4. Avalon-ST 256-Bit TX Interface x
6.1.4.1. Avalon-ST TX Three- and Four-Dword TLPs 6.1.4.2. Avalon-ST TX Interface tx_st_ready Deassertion 6.1.4.3. Assertion and Deassertion of Avalon-ST TX Interface tx_st_valid
6.1.12. Interrupts x
6.1.12.1. MSI and Legacy Interrupts
6.1.23. Message Handling x
6.1.23.1. Endpoint Received Messages 6.1.23.2. Endpoint Transmitted Messages
6.2. Errors reported by the Application Layer x
6.2.1. Error Handling
6.3. Power Management x
6.3.1. Endpoint D3 Entry 6.3.2. End Point D3 Exit 6.3.3. Exit from D3 hot 6.3.4. Exit from D3 cold 6.3.5. Active State Power Management
6.4. Transaction Ordering x
6.4.1. TX TLP Ordering 6.4.2. RX TLP Ordering
6.5. RX Buffer x
6.5.1. Retry Buffer 6.5.2. Configuration Retry Status
7. Interrupts x
7.1. Interrupts for Endpoints
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Registers x
8.1. Configuration Space Registers
8.1. Configuration Space Registers x
8.1.1. Register Access Definitions 8.1.2. PCI Configuration Header Registers 8.1.3. PCI Express Capability Structures 8.1.4. Intel Defined VSEC Capability Header 8.1.5. General Purpose Control and Status Register 8.1.6. Uncorrectable Internal Error Status Register 8.1.7. Uncorrectable Internal Error Mask Register 8.1.8. Correctable Internal Error Status Register 8.1.9. Correctable Internal Error Mask Register 8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.4. Intel Defined VSEC Capability Header x
8.1.4.1. Intel Defined Vendor Specific Header 8.1.4.2. Intel Marker 8.1.4.3. JTAG Silicon ID 8.1.4.4. User Configurable Device and Board ID
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map x
8.1.10.1. ARI Enhanced Capability Header 8.1.10.2. SR-IOV Enhanced Capability Registers 8.1.10.3. Initial VFs and Total VFs Registers 8.1.10.4. VF Device ID Register 8.1.10.5. Page Size Registers 8.1.10.6. VF Base Address Registers (BARs) 0-5 8.1.10.7. Secondary PCI Express Extended Capability Header 8.1.10.8. Lane Status Registers 8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header 8.1.10.10. TPH Requester Capability Register 8.1.10.11. TPH Requester Control Register 8.1.10.12. Address Translation Services ATS Enhanced Capability Header 8.1.10.13. ATS Capability Register and ATS Control Register
9. Testbench and Design Example x
9.1. Endpoint Testbench 9.2. Test Driver Module 9.3. Root Port BFM Overview 9.4. BFM Procedures and Functions
9.1. Endpoint Testbench x
9.1.1. Endpoint Testbench for SR-IOV
9.3. Root Port BFM Overview x
9.3.1. BFM Memory Map 9.3.2. Configuration Space Bus and Device Numbering 9.3.3. Configuration of Root Port and Endpoint 9.3.4. Issuing Read and Write Transactions to the Application Layer
9.4. BFM Procedures and Functions x
9.4.1. ebfm_barwr Procedure 9.4.2. ebfm_barwr_imm Procedure 9.4.3. ebfm_barrd_wait Procedure 9.4.4. ebfm_barrd_nowt Procedure 9.4.5. ebfm_cfgwr_imm_wait Procedure 9.4.6. ebfm_cfgwr_imm_nowt Procedure 9.4.7. ebfm_cfgrd_wait Procedure 9.4.8. ebfm_cfgrd_nowt Procedure 9.4.9. BFM Configuration Procedures 9.4.10. BFM Shared Memory Access Procedures 9.4.11. BFM Log and Message Procedures 9.4.12. Verilog HDL Formatting Functions
9.4.9. BFM Configuration Procedures x
9.4.9.1. ebfm_cfg_rp_ep Procedure 9.4.9.2. ebfm_cfg_decode_bar Procedure
9.4.10. BFM Shared Memory Access Procedures x
9.4.10.1. Shared Memory Constants 9.4.10.2. shmem_write Task 9.4.10.3. shmem_read Function 9.4.10.4. shmem_display Verilog HDL Function 9.4.10.5. shmem_fill Procedure 9.4.10.6. shmem_chk_ok Function
9.4.11. BFM Log and Message Procedures x
9.4.11.1. ebfm_display Verilog HDL Function 9.4.11.2. ebfm_log_stop_sim Verilog HDL Function 9.4.11.3. ebfm_log_set_suppressed_msg_mask Task 9.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 9.4.11.5. ebfm_log_open Verilog HDL Function 9.4.11.6. ebfm_log_close Verilog HDL Function
9.4.12. Verilog HDL Formatting Functions x
9.4.12.1. himage1 9.4.12.2. himage2 9.4.12.3. himage4 9.4.12.4. himage8 9.4.12.5. himage16 9.4.12.6. dimage1 9.4.12.7. dimage2 9.4.12.8. dimage3 9.4.12.9. dimage4 9.4.12.10. dimage5 9.4.12.11. dimage6 9.4.12.12. dimage7
10. Document Revision History x
10.1. Document Revision History for the Intel® L- and H-Tile Avalon® Streaming and Single-Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
D. Troubleshooting and Observing the Link Status x
D.1. Troubleshooting D.2. PCIe Link Inspector Overview
D.1. Troubleshooting x
D.1.1. Simulation Fails To Progress Beyond Polling.Active State D.1.2. Hardware Bring-Up Issues D.1.3. Link Training D.1.4. Link Hangs in L0 State D.1.5. Use Third-Party PCIe Analyzer
D.2. PCIe Link Inspector Overview x
D.2.1. PCIe* Link Inspector Hardware
D.2.1. PCIe* Link Inspector Hardware x
D.2.1.1. Enabling the PCIe* Link Inspector D.2.1.2. Launching the PCIe* Link Inspector D.2.1.3. The PCIe* Link Inspector LTSSM Monitor D.2.1.4. Accessing the Configuration Space and Transceiver Registers D.2.1.5. Additional Status Commands
D.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
D.2.1.3.1. LTSSM Monitor Registers D.2.1.3.2. ltssm_save2file <file_name> D.2.1.3.3. ltssm_file2console D.2.1.3.4. ltssm_debug_check D.2.1.3.5. ltssm_display <num_states> D.2.1.3.6. ltssm_save_oldstates
D.2.1.4. Accessing the Configuration Space and Transceiver Registers x
D.2.1.4.1. PCIe* Link Inspector Commands D.2.1.4.2. NPDME PLL and Channel Commands D.2.1.4.3. Register Address Map
D.2.1.5. Additional Status Commands x
D.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Document Revision History
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Troubleshooting and Observing the Link Status

9.3.3. Configuration of Root Port and Endpoint

Before you issue transactions to the Endpoint, you must configure the Root Port and Endpoint Configuration Space registers.

The ebfm_cfg_rp_ep procedure executes the following steps to initialize the Configuration Space:

  1. Sets the Root Port Configuration Space to enable the Root Port to send transactions on the PCI Express link.
  2. Sets the Root Port and Endpoint PCI Express Capability Device Control registers as follows:
    1. Disables Error Reporting in both the Root Port and Endpoint. The BFM does not have error handling capability.
    2. Enables Relaxed Ordering in both Root Port and Endpoint.
    3. Enables Extended Tags for the Endpoint if the Endpoint has that capability.
    4. Disables Phantom Functions, Aux Power PM, and No Snoop in both the Root Port and Endpoint.
    5. Sets the Max Payload Size to the value that the Endpoint supports because the Root Port supports the maximum payload size.
    6. Sets the Root Port Max Read Request Size to 4 KB because the example Endpoint design supports breaking the read into as many completions as necessary.
    7. Sets the Endpoint Max Read Request Size equal to the Max Payload Size because the Root Port does not support breaking the read request into multiple completions.
  3. Assigns values to all the Endpoint BAR registers. The BAR addresses are assigned by the algorithm outlined below.
    1. I/O BARs are assigned smallest to largest starting just above the ending address of BFM shared memory in I/O space and continuing as needed throughout a full 32-bit I/O space.
    2. The 32-bit non-prefetchable memory BARs are assigned smallest to largest, starting just above the ending address of BFM shared memory in memory space and continuing as needed throughout a full 32-bit memory space.
    3. The value of the addr_map_4GB_limit input to the ebfm_cfg_rp_ep procedure controls the assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS. The default value of the addr_map_4GB_limit is 0.

      If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep procedure is set to 0, then the ebfm_cfg_rp_ep procedure assigns the 32‑bit prefetchable memory BARs largest to smallest, starting at the top of 32-bit memory space and continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR.

      However, if the addr_map_4GB_limit input is set to 1, the address map is limited to 4 GB. The ebfm_cfg_rp_ep procedure assigns 32-bit and 64-bit prefetchable memory BARs largest to smallest, starting at the top of the 32-bit memory space and continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR.

    4. If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep procedure is set to 0, then the ebfm_cfg_rp_ep procedure assigns the 64-bit prefetchable memory BARs smallest to largest starting at the 4 GB address assigning memory ascending above the 4 GB limit throughout the full 64-bit memory space.

      If the addr_map_4 GB_limit input to the ebfm_cfg_rp_ep procedure is set to 1, the ebfm_cfg_rp_ep procedure assigns the 32-bit and the 64-bit prefetchable memory BARs largest to smallest starting at the 4 GB address and assigning memory by descending below the 4 GB address to memory addresses as needed down to the ending address of the last 32-bit non-prefetchable BAR.

      The above algorithm cannot always assign values to all BARs when there are a few very large (1 GB or greater) 32-bit BARs. Although assigning addresses to all BARs may be possible, a more complex algorithm would be required to effectively assign these addresses. However, such a configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs, it displays an error message and stops the simulation.

  4. Based on the above BAR assignments, the ebfm_cfg_rp_ep procedure assigns the Root Port Configuration Space address windows to encompass the valid BAR address ranges.
  5. The ebfm_cfg_rp_ep procedure enables master transactions, memory address decoding, and I/O address decoding in the Endpoint PCIe* control register.

The ebfm_cfg_rp_ep procedure also sets up a bar_table data structure in BFM shared memory that lists the sizes and assigned addresses of all Endpoint BARs. This area of BFM shared memory is write-protected. Consequently, any application logic write accesses to this area cause a fatal simulation error.

BFM procedure calls to generate full PCIe* addresses for read and write requests to particular offsets from a BAR use this data structure. This procedure allows the testbench code that accesses the Endpoint application logic to use offsets from a BAR and avoid tracking specific addresses assigned to the BAR. The following table shows how to use those offsets.

Table 87.  BAR Table Structure

Offset (Bytes)

Description

+0

PCI Express address in BAR0

+4

PCI Express address in BAR1

+8

PCI Express address in BAR2

+12

PCI Express address in BAR3

+16

PCI Express address in BAR4

+20

PCI Express address in BAR5

+24

PCI Express address in Expansion ROM BAR

+28

Reserved

+32

BAR0 read back value after being written with all 1’s (used to compute size)

+36

BAR1 read back value after being written with all 1’s

+40

BAR2 read back value after being written with all 1’s

+44

BAR3 read back value after being written with all 1’s

+48

BAR4 read back value after being written with all 1’s

+52

BAR5 read back value after being written with all 1’s

+56

Expansion ROM BAR read back value after being written with all 1’s

+60

Reserved

The configuration routine does not configure any advanced PCI Express capabilities such as the AER capability.

Besides the ebfm_cfg_rp_ep procedure in altpcietb_bfm_rp_gen3_x8.sv, routines to read and write Endpoint Configuration Space registers directly are available in the Verilog HDL include file. After the ebfm_cfg_rp_ep procedure runs the PCI Express I/O and Memory Spaces have the layout shown in the following three figures. The memory space layout depends on the value of the addr_map_4GB_limit input parameter. The following figure shows the resulting memory space map when the addr_map_4GB_limit is 1.

Figure 72. Memory Space Layout—4 GB Limit

The following figure shows the resulting memory space map when the addr_map_4GB_limit is 0.

Figure 73. Memory Space Layout—No Limit

The following figure shows the I/O address space.

Figure 74. I/O Address Space
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