E-Tile JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. E-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the E-Tile JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. E-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide

5.1. JESD204C TX and RX Reset Sequence

The JESD204C base core and transport layer require various resets for the IP and transceiver. All the resets in the core assert asynchronously and deassert synchronously.

Table 17.   JESD204C IP Resets
Reset Signal Clock Domain Description

TX/RX Link and Frame Reset

j204c_tx_rst_n

j204c_rx_rst_n

TX/RX link clock
  • You can deassert the link and frame reset after the configuration phase completes.
  • After this reset deasserts, the JESD204C IP is in operation mode.
TX/RX frame clock

TX/RX PHY Reset

j204c_tx_phy_rst_n

j204c_rx_phy_rst_n

Transceiver Native PHY clock
  • The transceiver requires this reset to reset the PMA and PCS blocks.
  • Intel recommends that you assert the link and frame reset when this reset asserts.

TX/RX AVS Reset

j204c_tx_avs_rst_n

j204c_rx_avs_rst_n

TX/RX Avalon® memory-mapped reset for CSR

(j204c_tx_avs_clk/j204c_rx_avs_clk)

  • This reset is for the Avalon® memory-mapped slave interface, which consists of the Configuration and Status Register (CSR) blocks.
  • This reset must deassert first before the JESD204C IP link reset and frame reset deassert.
  • After this reset deasserts, configuration phase starts. You can program the CSR register values if a non-default value is required.
  • Intel recommends that you assert the link and frame reset when this reset asserts.
Figure 9.  JESD204C TX/RX Reset Sequence

The descriptions below correspond to the Figure 9:

  1. The sequence begins when the TX/RX AVS reset and TX/RX PHY reset deassert.
  2. During the configuration phase, you can configure the run-time CSR parameters. The number of clock cycles does not matter provided that j204c_tx_rst_n/j204c_rx_rst_n remains asserted.
  3. j204c_tx_rst_n/j204c_rx_rst_n only deasserts after configuration phase, and when the PLL is locked and the transceiver is ready. Internally, in the JESD204C IP, j204c_tx_rst_n/j204c_rx_rst_n synchronizes to the respective clock domains. You can assert j204c_tx_rst_n/j204c_rx_rst_n at any time after its initial deassertion, but when you deassert, make sure the configuration phase is over, the PLL is locked, and the transceiver is ready.
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