E-Tile JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. E-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the E-Tile JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. E-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide

4.4. JESD204C IP Component Files

The following table describes the generated files and other files that may be in your project directory. The names and types of generated files specified may vary depending on whether you create your design with VHDL or Verilog HDL.

Table 16.  Generated Files

Extension

Description

<variation name>.v or .vhd

IP core variation file, which defines a VHDL or Verilog HDL description of the custom IP. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Intel® Quartus® Prime software.

<variation name>.cmp

A VHDL component declaration file for the IP variation. Add the contents of this file to any VHDL architecture that instantiates the IP.

<variation name>.sdc

Contains timing constraints for your IP variation.

<variation name>.qip or .ip

Contains Intel® Quartus® Prime project information for your IP variation.

<variation name>.tcl

Tcl script file to run in Intel® Quartus® Prime software.

<variation name>.sip

Contains IP library mapping information required by the Intel® Quartus® Prime software. The Intel® Quartus® Prime software generates a . sip file during generation of some Intel® FPGA IP cores. You must add any generated .sip file to your project for use by NativeLink simulation and the Intel® Quartus® Prime Archiver.

<variation name>.spd

Contains a list of required simulation files for your IP.

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