5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 3/29/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Document Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Document Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

4.1. 5G LDPC Decoder

The 5G LDPC Decoder supports all modes specified in the 3GPP New Radio specification. The decoder can be either a single decoder or dual decoders.

Input packets arbitration for dual decoders:

  • If the incoming packet has small Z, the IP sends it to the second decoder, if it is available. If the second decoder is full and not available to process the small packet, the IP sends the small packet to the first decoder, if it is available. If none of the two decoders are available for the small packet, the IP back pressures to the upstream
  • If the incoming packet has large Z, the IP sends it to the first decoder, if it is available. If the first decoder is full and not available to process this packet, the IP back pressures to the upstream. Even if the upstream has the subsequent packet that has small Z and the second decoder is available to process it, the packet doesn't arrive at the IP until the first decoder becomes available to process the previous big packet

The order of output decoded packets is in the order that the IP receives the packets, although the IP processes the packets out of order.


Section Content
5G LDPC Decoder Signals
5G LDPC Decoder Data Formats
5G LDPC IP Decoder Parameters

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