5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats Input Data Format Decoder Input LLR Symbol Format Decoder Input Control and Output Status Signal Formats Decoder Output Data Format 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

4.1.2. 5G LDPC Decoder Data Formats

Input Data Format

An input code block of length N consists of N log-likelihood ratio codes (LLRs): L0,L1,L2,...,LN-1. Each LLR is IN_WIDTH bits wide.

IN_WIDTH is 5 or 6. The decoder input on a single active edge of the clock is 64 LLRs. The resulting width of the input data bus to the decoder is 64*IN_WIDTH.

The decoder IP accepts punctured LLRs. You can assume that the IP punctures the first 2*Z bits of the original information block during encoding, where Z is the lifting size. The IP functionally prepends 2*Z implicit LLRs with value IN_WIDTH'b0 to the input stream of LLRs.

The number of clock cycles that the IP requires to receive the LLR values is (nb - 2) * ceil(Z / 64), where nb is the number of columns in the parity check matrix. The value of nb depends on the base graph, the information block size K, and the code rate.

Table 13.  Example: Decoder Input Data Format for Base Graph 1, Z=384, and Code Rate 8/9

In this example, nb=27. Therefore, the IP requires (27-2)*ceil(384/64) = 150 clock cycles to receive the input data.

sink_data[64*IN_WIDTH-1:0] =

sink_data[383:0]

 clock cycle
0 1 ... 148 149
sink_data[5:0] L0 L64 ... L9472 L9536
sink_data[11:6] L1 L65 ... L9473 L9537
... ... ... ... ... ...
sink_data[383:378] L63 L127 ... L9535 L9599
Table 14.  Example 2: Decoder Input Data Format for Base Graph 2, Z=208, and Code Rate=1/2In this example, nb=22. Therefore, the IP requires (22-2)*ceil(208/64) = 80 clock cycles to receive the input data, where cells with X indicate the bits to ignore. Each 208 LLR symbols take four clock cycles to receive by the IP.
sink_data[64*IN_WIDTH-1:0] clock cycle
0 1 2 3 4 5 6 7 … 78 79
sink_data[1*IN_WIDTH-1:0*IN_WIDTH] L0 L64 L128 L192 L208 L272 L336 L400 … L4080 L4144
… … … … … … … … … … … …
sink_data[16*IN_WIDTH-1:15*IN_WIDTH] L15 L79 L143 L207 L223 L287 L351 L415 … L4095 L4159
sink_data[17*IN_WIDTH-1:16*IN_WIDTH] L16 L80 L144 X L224 L288 L352 X … L4096 X
… … … … X … … … X … … X
sink_data[64*IN_WIDTH-1:63*IN_WIDTH] L63 L127 L191 X L271 L335 L399 X … L4143 X

Decoder Input LLR Symbol Format

The log-likelihood value is the logarithm of the probability that the received bit is a 0, divided by the probability that this bit is a 1. It is represented as a two’s complement number. A value of zero indicates equal probability of a 1 and a 0, which you should use for depuncturing. The decoder uses asymmetrical numeric range for LLRs including the most negative two's complement value for the chosen number of bits.

Table 15.  LLR Meaning
LLR (IN_WIDTH=6) Meaning

Resulting Hard Decision

011111 Most likelihood of a 0 0
... ... ...
000001 Lowest likelihood of a 0 0
000000 Equal probability of a 0 or 1 1 (the convention implemented by the decoder)
111111 Lowest likelihood of a 1 1
... ... ...
100000 Most likelihood of a 1 1

Decoder Input Control and Output Status Signal Formats

The input mode signal, sink_mode[11:0], and the output mode signal, source_mode[11:0], have the same fields. The required input values on sink_mode are the expected output values on source_mode.

  • sink_mode[11] encodes the base graph selection. The value of 0 indicates base graph 1 (BG1), and the value of 1 indicates base graph 2 (BG2).
  • sink_mode[10:8] is code rate selection. Refer to Table 17.
  • sink_mode[7] is enable reduced-syndrome . 0: disable; 1: enable.
  • sink_mode[6] is disable early termination . 0: enable; 1: disable.
  • sink_mode[5:0] is Z selection. Refer to Table 16.
Table 16.  Z Selection sink_mode[5:0]
sink_mode[5:0] Z sink_mode[5:0] Z
0 2 26 48
1 3 27 52
2 4 28 56
3 5 29 60
4 6 30 64
5 7 31 72
6 8 32 80
7 9 33 88
8 10 34 96
9 11 35 104
10 12 36 112
11 13 37 120
12 14 38 128
13 15 39 144
14 16 40 160
15 18 41 176
16 20 42 192
17 22 43 208
18 24 44 224
19 26 45 240
20 28 46 256
21 30 47 288
22 32 48 320
23 36 49 352
24 40 50 384
25 44 X X
Table 17.  Code Rate Selection (sink_mode[10:8])The numbers are in terms of circulant matrix blocks.
sink_mode[10:8]

Code Rate Base Graph 1 Base Graph 2
Number of Rows in Parity Check Matrix (mb) Number of Columns in Parity Check Matrix (nb) Number of Rows in Parity Check Matrix (mb) Number of Columns in Parity Check matrix (nb)
000 1/5 X X 42 52
001 1/3 46 68 22 32
010 2/5 35 57 17 27
011 1/2 24 46 12 22
100 2/3 13 35 7 17
101 22/30 (~3/4) 10 32 X X
110 22/27 (~5/6) 7 29 X X
111 22/25 (~8/9) 5 27 X X

Decoder Output Data Format

The width of the source_data[383:0] signal is 384 bits, where only the Z LSBs are valid. You can ignore the rest of the MSBs.The number of output block bits is 22*Z for BG1 and 10*Z for BG2. Hence, the IP requires 22 clock cycles for BG1 and 10 clock cycles for BG2 to output the data.

Table 18.  Decoder Output Data Format for Base Graph 1, Z=384

source_data[383:0]

 Clock Cycle
0 1 ... 20 21
source_data[0] b0 b384 ... b7680 b8064
source_data[1] b1 b385 ... b7681 b8065
... ... ... ... ... ...
source_data[383] b383 b767 ... b8063 b8447
Table 19.  Decoder Output Data Format for Base Graph 2, Z=208The IP requires 10 clock cycles to output the data.
source_data[383:0] Clock Cycle
0 1 ... 8 9
source_data[0] b0 b208 ... b1664 b1872
... ... ... ... ... ...
source_data[207] b207 b415 ... b1871 b2079
source_data[208] Ignored
...
source_data[383]
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