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1.1. IP Catalog and Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores
1.3. Best Practices for Intel® FPGA IP
1.4. IP General Settings
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.7. Modifying an IP Variation
1.8. Upgrading IP Cores
1.9. Simulating Intel® FPGA IP Cores
1.10. Synthesizing IP Cores in Other EDA Tools
1.11. Support for the IEEE 1735 Encryption Standard
1.12. Introduction to Intel® FPGA IP Cores Archives
1.13. Introduction to Intel® FPGA IP Cores Revision History
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts
1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
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1.10.1.1. Accessing HDL Code Templates
The Intel® Quartus® Prime software includes code examples or templates for inferred RAMs, ROMs, shift registers, arithmetic functions, and DSP functions optimized for Intel FPGA devices. To access HDL code templates to define these IP cores in HDL:
- Open a file in the text editor.
- Click Edit > Insert template.
- In the Insert Template dialog box, click the + icon to expand either the Verilog HDL category or the VHDL category, depending on the HDL you prefer.
- Under Full Designs, expand the navigation tree to display the type of functions you want to infer.
- Select the function to display the code in the Preview pane and click Insert.