Visible to Intel only — GUID: mwh1409958306183
Ixiasoft
1.1. IP Catalog and Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores
1.3. Best Practices for Intel® FPGA IP
1.4. IP General Settings
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.7. Modifying an IP Variation
1.8. Upgrading IP Cores
1.9. Simulating Intel® FPGA IP Cores
1.10. Synthesizing IP Cores in Other EDA Tools
1.11. Support for the IEEE 1735 Encryption Standard
1.12. Introduction to Intel® FPGA IP Cores Archives
1.13. Introduction to Intel® FPGA IP Cores Revision History
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts
1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
Visible to Intel only — GUID: mwh1409958306183
Ixiasoft
1.10.1.1.2. Example Top-Level VHDL Module
VHDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity MF_top is
port (clock, sel : in std_logic;
a, b, datab : in std_logic_vector(31 downto 0);
result : out std_logic_vector(31 downto 0));
end entity;
architecture arch_MF_top of MF_top is
signal wire_dataa : std_logic_vector(31 downto 0);
begin
wire_dataa <= a when (sel = '1') else b;
inst1 : altfp_mult
generic map (
pipeline => 11,
width_exp => 8,
width_man => 23,
exception_handling => "no")
port map (
dataa => wire_dataa,
datab => datab,
clock => clock,
result => result);
end arch_MF_top;