Introduction to Altera® IP Cores

ID 683102
Date 3/31/2025
Public
Document Table of Contents

1.12.2.3. Using Partial Encryption

By default, both encryptor modes fully encrypt the provided source file. However, by using special pragmas in your source file, you can specify that only certain portions of your file are encrypted or unencrypted. There are different partial encryption pragmas each language:

Verilog HDL Pragma

`pragma protect begin
`pragma protect end

VHDL Code Block

`protect begin
`protect end

Code between these pragmas is encrypted, while code outside the pragmas is left in plaintext. There can be multiple sections of encrypted code scattered throughout a file. The following Verilog HDL code shows an example:

module hello_world;
initial begin
   `pragma protect begin
   $display(“Hello World”);
   `pragma protect end
   $finish
end
endmodule

These pragmas result in $display(“Hello World”) becoming encrypted, while the rest of the module is written out as plaintext. You can use partial encryption with either Quartus or Supported Simulator Modes. The command usage is as follows:

encrypt_1735 --simulation --language=verilog some_file.v