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1.1. Altera IP Catalog and Parameter Editor
1.2. Installing and Licensing Altera* IP Cores
1.3. Best Practices for Altera* IP
1.4. IP General Settings
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Quartus® Prime Standard Edition)
1.7. Generating Example Designs for Altera* IP
1.8. Modifying an IP Variation
1.9. Upgrading IP Cores
1.10. Simulating Altera* IP Cores
1.11. Synthesizing IP Cores in Other EDA Tools
1.12. Support for the IEEE 1735 Encryption Standard
1.13. Introduction to Altera* IP Cores Revision History
1.14. Introduction to Altera* IP Cores Archives
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts
1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts
1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
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1.12.2.3. Using Partial Encryption
By default, both encryptor modes fully encrypt the provided source file. However, by using special pragmas in your source file, you can specify that only certain portions of your file are encrypted or unencrypted. There are different partial encryption pragmas each language:
Verilog HDL Pragma
`pragma protect begin `pragma protect end
VHDL Code Block
`protect begin `protect end
Code between these pragmas is encrypted, while code outside the pragmas is left in plaintext. There can be multiple sections of encrypted code scattered throughout a file. The following Verilog HDL code shows an example:
module hello_world; initial begin `pragma protect begin $display(“Hello World”); `pragma protect end $finish end endmodule
These pragmas result in $display(“Hello World”) becoming encrypted, while the rest of the module is written out as plaintext. You can use partial encryption with either Quartus or Supported Simulator Modes. The command usage is as follows:
encrypt_1735 --simulation --language=verilog some_file.v