Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

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ID 683093
Date 5/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Stratix V Hard IP for PCI Express 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design 4. Parameter Settings 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Transceiver PHY IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Avalon-ST Example Designs 1.6. Debug Features 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet x
1.1.1. Features
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Stratix V Hard IP for PCI Express x
2.1. Qsys Design Flow
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Simulation Log File Generation 2.1.6. Understanding Physical Placement of the PCIe IP Core 2.1.7. Compiling the Design in the Qsys Design Flow 2.1.8. Modifying the Example Design 2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design x
3.1. Copying the Configuration Space Bypass Mode Example Design 3.2. Generating the Qsys System 3.3. Simulating the Example Design
3.2. Generating the Qsys System x
3.2.1. Generating Synthesis Files 3.2.2. Understanding the Generated Files 3.2.3. Understanding Simulation Log File Generation
3.3. Simulating the Example Design x
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface 3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface 3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface 3.3.4. Partial Transcript for Configuration Space Bypass Simulation
4. Parameter Settings x
4.1. System Settings 4.2. Base Address Register (BAR) and Expansion ROM Settings 4.3. Base and Limit Registers for Root Ports 4.4. Device Identification Registers 4.5. PCI Express and PCI Capabilities Parameters 4.6. Vendor Specific Extended Capability (VSEC) 4.7. PHY Characteristics
4.5. PCI Express and PCI Capabilities Parameters x
4.5.1. PCI Express and PCI Capabilities 4.5.2. Error Reporting 4.5.3. Link Capabilities 4.5.4. MSI and MSI-X Capabilities 4.5.5. Slot Capabilities 4.5.6. Power Management
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Configuration Space Bypass Mode Interface Signals 5.9. Parity Signals 5.10. LMI Signals 5.11. Transaction Layer Configuration Space Signals 5.12. Hard IP Reconfiguration Interface 5.13. Power Management Signals 5.14. Physical Layer Interface Signals
5.11. Transaction Layer Configuration Space Signals x
5.11.1. Configuration Space Register Access Timing 5.11.2. Configuration Space Register Access
5.14. Physical Layer Interface Signals x
5.14.1. Transceiver Reconfiguration 5.14.2. Serial Data Signals 5.14.3. PIPE Interface Signals 5.14.4. Test Signals
5.14.2. Serial Data Signals x
5.14.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 5.14.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. Uncorrectable Internal Error Mask Register 6.8. Uncorrectable Internal Error Status Register 6.9. Correctable Internal Error Mask Register 6.10. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Transceiver Reconfiguration 9.1.6. Interrupts 9.1.7. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space 9.2.2. Configuration Space Bypass Mode
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Analog QSF Assignments Using the Assignment Editor 12.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.3. Recommended Reset Sequence to Avoid Link Training Issues 12.4. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Transceiver PHY IP Reconfiguration x
15.1. Connecting the Transceiver Reconfiguration Controller IP Core 15.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Root Port Testbench 16.3. Test Driver Module 16.4. Root Port Design Example 16.5. Root Port BFM Overview 16.6. BFM Procedures and Functions 16.7. Setting Up Simulation
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.5. Root Port BFM Overview x
16.5.1. BFM Memory Map 16.5.2. Configuration Space Bus and Device Numbering 16.5.3. Configuration of Root Port and Endpoint 16.5.4. Issuing Read and Write Transactions to the Application Layer
16.6. BFM Procedures and Functions x
16.6.1. ebfm_barwr Procedure 16.6.2. ebfm_barwr_imm Procedure 16.6.3. ebfm_barrd_wait Procedure 16.6.4. ebfm_barrd_nowt Procedure 16.6.5. ebfm_cfgwr_imm_wait Procedure 16.6.6. ebfm_cfgwr_imm_nowt Procedure 16.6.7. ebfm_cfgrd_wait Procedure 16.6.8. ebfm_cfgrd_nowt Procedure 16.6.9. BFM Configuration Procedures 16.6.10. BFM Shared Memory Access Procedures 16.6.11. BFM Log and Message Procedures 16.6.12. Verilog HDL Formatting Functions
16.6.9. BFM Configuration Procedures x
16.6.9.1. ebfm_cfg_rp_ep Procedure 16.6.9.2. ebfm_cfg_decode_bar Procedure
16.6.10. BFM Shared Memory Access Procedures x
16.6.10.1. Shared Memory Constants 16.6.10.2. shmem_write Task 16.6.10.3. shmem_read Function 16.6.10.4. shmem_display Verilog HDL Function 16.6.10.5. shmem_fill Procedure 16.6.10.6. shmem_chk_ok Function
16.6.11. BFM Log and Message Procedures x
16.6.11.1. ebfm_display Verilog HDL Function 16.6.11.2. ebfm_log_stop_sim Verilog HDL Function 16.6.11.3. ebfm_log_set_suppressed_msg_mask Task 16.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.6.11.5. ebfm_log_open Verilog HDL Function 16.6.11.6. ebfm_log_close Verilog HDL Function
16.6.12. Verilog HDL Formatting Functions x
16.6.12.1. himage1 16.6.12.2. himage2 16.6.12.3. himage4 16.6.12.4. himage8 16.6.12.5. himage16 16.6.12.6. dimage1 16.6.12.7. dimage2 16.6.12.8. dimage3 16.6.12.9. dimage4 16.6.12.10. dimage5 16.6.12.11. dimage6 16.6.12.12. dimage7
16.7. Setting Up Simulation x
16.7.1. Changing Between Serial and PIPE Simulation 16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 16.7.3. Viewing the Important PIPE Interface Signals 16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 16.7.6. Changing between the Hard and Soft Reset Controller
17. Debugging x
17.1. Hardware Bring-Up Issues 17.2. Link Training 17.3. Use Third-Party PCIe Analyzer 17.4. BIOS Enumeration Issues
17.2. Link Training x
17.2.1. Debugging Link that Fails To Reach L0 17.2.2. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History Stratix V Avalon® -ST Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Stratix V Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

11. Throughput Optimization

The PCI Express Base Specification defines a flow control mechanism to ensure efficient transfer of TLPs.

Each transmitter, the write requester in this case, maintains a credit limit register and a credits consumed register. The credit limit register is the sum of all credits received by the receiver, the write completer in this case. The credit limit register is initialized during the flow control initialization phase of link initialization and then updated during operation by Flow Control (FC) Update DLLPs. The credits consumed register is the sum of all credits consumed by packets transmitted. Separate credit limit and credits consumed registers exist for each of the six types of Flow Control:

  • Posted Headers
  • Posted Data
  • Non-Posted Headers
  • Non-Posted Data
  • Completion Headers
  • Completion Data

Each receiver also maintains a credit allocated counter which is initialized to the total available space in the RX buffer (for the specific Flow Control class) and then incremented as packets are pulled out of the RX buffer by the Application Layer. The value of this register is sent as the FC Update DLLP value.

Figure 52. Flow Control Update Loop

The PCIe Hard IP maintains its own flow control logic, including a credit consumed register, and ensures that no TLP is sent that would use more credits than are available for that type of TLP. If you want optimum performance and granularity, you can maintain your own credit consumed register and flow control gating logic for each credit category (Header/Data, Posted/Non-posted/Completion). This allows you to halt the transmission of TLPs for a category that is out of credits, while still allowing TLP transmission for categories that have sufficient credits.

The following steps describe the Flow Control Update loop. The corresponding numbers in the figure show the general area to which they correspond.

  1. When the Application Layer has a packet to transmit, the number of credits required is calculated. If the required credits are less than or equal to the current value of available credits (credit limit - credits consumed so far), then the packet can be transmitted immediately. However, if the credit limit minus credits consumed is less than the required credits, then the packet must be held until the credit limit is increased to a sufficient value by an FC Update DLLP. This check is performed separately for the header and data credits; a single packet consumes only a single header credit.
  2. After the packet is selected for transmission the credits consumed register is incremented by the number of credits consumed by this packet. This increment happens for both the header and data credit consumed registers.
  3. The packet is received at the other end of the link and placed in the RX buffer.
  4. At some point the packet is read out of the RX buffer by the Application Layer. After the entire packet is read out of the RX buffer, the credit allocated register can be incremented by the number of credits the packet has used. There are separate credit allocated registers for the header and data credits.
  5. The value in the credit allocated register is used to create an FC Update DLLP.
  6. After an FC Update DLLP is created, it arbitrates for access to the PCI Express link. The FC Update DLLPs are typically scheduled with a low priority; consequently, a continuous stream of Application Layer TLPs or other DLLPs (such as ACKs) can delay the FC Update DLLP for a long time. To prevent starving the attached transmitter, FC Update DLLPs are raised to a high priority under the following three circumstances:
    1. When the last sent credit allocated counter minus the amount of received data is less than MAX_PAYLOAD and the current credit allocated counter is greater than the last sent credit counter. Essentially, this means the data sink knows the data source has less than a full MAX_PAYLOAD worth of credits, and therefore is starving.
    2. When an internal timer expires from the time the last FC Update DLLP was sent, which is configured to 30 µs to meet the PCI Express Base Specification for resending FC Update DLLPs.
    3. When the credit allocated counter minus the last sent credit allocated counter is greater than or equal to 25% of the total credits available in the RX buffer, then the FC Update DLLP request is raised to high priority.

      After arbitrating, the FC Update DLLP that won the arbitration to be the next item is transmitted. In the worst case, the FC Update DLLP may need to wait for a maximum sized TLP that is currently being transmitted to complete before it can be sent.

  7. The original write requester receives the FC Update DLLP. The credit limit value is updated. If packets are stalled waiting for credits, they can now be transmitted.
Note: You must keep track of the credits consumed by the Application Layer.

Section Content
Throughput of Posted Writes
Throughput of Non-Posted Reads

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