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1. Datasheet
2. Getting Started with the Stratix V Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History
2.1.1. Generating the Testbench
2.1.2. Simulating the Example Design
2.1.3. Generating Synthesis Files
2.1.4. Understanding the Files Generated
2.1.5. Understanding Simulation Log File Generation
2.1.6. Understanding Physical Placement of the PCIe IP Core
2.1.7. Compiling the Design in the Qsys Design Flow
2.1.8. Modifying the Example Design
2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface
3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface
3.3.4. Partial Transcript for Configuration Space Bypass Simulation
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Configuration Space Bypass Mode Interface Signals
5.9. Parity Signals
5.10. LMI Signals
5.11. Transaction Layer Configuration Space Signals
5.12. Hard IP Reconfiguration Interface
5.13. Power Management Signals
5.14. Physical Layer Interface Signals
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. CvP Registers
6.7. Uncorrectable Internal Error Mask Register
6.8. Uncorrectable Internal Error Status Register
6.9. Correctable Internal Error Mask Register
6.10. Correctable Internal Error Status Register
16.6.1. ebfm_barwr Procedure
16.6.2. ebfm_barwr_imm Procedure
16.6.3. ebfm_barrd_wait Procedure
16.6.4. ebfm_barrd_nowt Procedure
16.6.5. ebfm_cfgwr_imm_wait Procedure
16.6.6. ebfm_cfgwr_imm_nowt Procedure
16.6.7. ebfm_cfgrd_wait Procedure
16.6.8. ebfm_cfgrd_nowt Procedure
16.6.9. BFM Configuration Procedures
16.6.10. BFM Shared Memory Access Procedures
16.6.11. BFM Log and Message Procedures
16.6.12. Verilog HDL Formatting Functions
16.7.1. Changing Between Serial and PIPE Simulation
16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
16.7.3. Viewing the Important PIPE Interface Signals
16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
16.7.6. Changing between the Hard and Soft Reset Controller
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16.5. Root Port BFM Overview
The basic Root Port BFM provides Verilog HDL task‑based interface to request transactions to issue on the PCI Express link. The Root Port BFM also handles requests received from the PCI Express link. The following figure shows the most important modules in the Root Port BFM.
Figure 59. Root Port BFM
These modules implement the following functionality:
- BFM Log Interface,altpcietb_bfm_log.v and altlpcietb_bfm_rp_<gen>_x8.v: The BFM log functions provides routine for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
- BFM Read/Write Request Functions, altpcietb_bfm_rp_<gen>_x8.sv: These functions provide the basic BFM calls for PCI Express read and write requests. For details on these procedures, refer to BFM Read and Write Procedures.
- BFM Log Interface, altpcietb_bfm_log.v and altlpcietb_bfm_rp_<gen>_x8.v: The BFM log functions provides routine for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
- BFM Configuration Functions, altpcietb_g3bfm_configure.v : These functions provide the BFM calls to request configuration of the PCI Express link and the Endpoint Configuration Space registers. For details on these procedures and functions, refer to BFM Configuration Procedures.
- BFM shared memory, altpcietb_g3bfm_shmem_common.v: This modules provides the Root Port BFM shared memory. It implements the following functionality:
- Provides data for TX write operations
- Provides data for RX read operations
- Receives data for RX write operations
- Receives data for received completions
- BFM Request Interface, altpcietb_g3bfm_req_intf.v: This interface provides the low-level interface between the altpcietb_g3bfm_rdwr and altpcietb_bfm_configure procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and the values programmed in the BAR registers of the Endpoint. It also stores other critical data used for internal BFM management. You do not need to access these files directly to adapt the testbench to test your Endpoint application.
- Avalon‑ST Interfaces, altpcietb_g3bfm_vc_intf_ast_common.v: These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express transactions. They handle completions received from the PCI Express link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express link, and store or fetch data from the shared memory before generating the required completions.