Stratix V Avalon-ST Interface for PCIe Solutions: User Guide

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ID 683093
Date 5/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Stratix V Hard IP for PCI Express 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design 4. Parameter Settings 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Transceiver PHY IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Avalon-ST Example Designs 1.6. Debug Features 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet x
1.1.1. Features
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Stratix V Hard IP for PCI Express x
2.1. Qsys Design Flow
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Simulation Log File Generation 2.1.6. Understanding Physical Placement of the PCIe IP Core 2.1.7. Compiling the Design in the Qsys Design Flow 2.1.8. Modifying the Example Design 2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design x
3.1. Copying the Configuration Space Bypass Mode Example Design 3.2. Generating the Qsys System 3.3. Simulating the Example Design
3.2. Generating the Qsys System x
3.2.1. Generating Synthesis Files 3.2.2. Understanding the Generated Files 3.2.3. Understanding Simulation Log File Generation
3.3. Simulating the Example Design x
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface 3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface 3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface 3.3.4. Partial Transcript for Configuration Space Bypass Simulation Transcript from ModelSim Simulation of Gen1 x4 Endpoint
4. Parameter Settings x
4.1. System Settings 4.2. Base Address Register (BAR) and Expansion ROM Settings 4.3. Base and Limit Registers for Root Ports 4.4. Device Identification Registers 4.5. PCI Express and PCI Capabilities Parameters 4.6. Vendor Specific Extended Capability (VSEC) 4.7. PHY Characteristics
4.5. PCI Express and PCI Capabilities Parameters x
4.5.1. PCI Express and PCI Capabilities 4.5.2. Error Reporting 4.5.3. Link Capabilities 4.5.4. MSI and MSI-X Capabilities 4.5.5. Slot Capabilities 4.5.6. Power Management
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Configuration Space Bypass Mode Interface Signals 5.9. Parity Signals 5.10. LMI Signals 5.11. Transaction Layer Configuration Space Signals 5.12. Hard IP Reconfiguration Interface 5.13. Power Management Signals 5.14. Physical Layer Interface Signals
5.11. Transaction Layer Configuration Space Signals x
5.11.1. Configuration Space Register Access Timing 5.11.2. Configuration Space Register Access
5.14. Physical Layer Interface Signals x
5.14.1. Transceiver Reconfiguration 5.14.2. Serial Data Signals 5.14.3. PIPE Interface Signals 5.14.4. Test Signals
5.14.2. Serial Data Signals x
5.14.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 5.14.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. Uncorrectable Internal Error Mask Register 6.8. Uncorrectable Internal Error Status Register 6.9. Correctable Internal Error Mask Register 6.10. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Transceiver Reconfiguration 9.1.6. Interrupts 9.1.7. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space 9.2.2. Configuration Space Bypass Mode
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Analog QSF Assignments Using the Assignment Editor 12.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.3. Recommended Reset Sequence to Avoid Link Training Issues 12.4. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Transceiver PHY IP Reconfiguration x
15.1. Connecting the Transceiver Reconfiguration Controller IP Core 15.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Root Port Testbench 16.3. Test Driver Module 16.4. Root Port Design Example 16.5. Root Port BFM Overview 16.6. BFM Procedures and Functions 16.7. Setting Up Simulation
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.5. Root Port BFM Overview x
16.5.1. BFM Memory Map 16.5.2. Configuration Space Bus and Device Numbering 16.5.3. Configuration of Root Port and Endpoint 16.5.4. Issuing Read and Write Transactions to the Application Layer
16.6. BFM Procedures and Functions x
16.6.1. ebfm_barwr Procedure 16.6.2. ebfm_barwr_imm Procedure 16.6.3. ebfm_barrd_wait Procedure 16.6.4. ebfm_barrd_nowt Procedure 16.6.5. ebfm_cfgwr_imm_wait Procedure 16.6.6. ebfm_cfgwr_imm_nowt Procedure 16.6.7. ebfm_cfgrd_wait Procedure 16.6.8. ebfm_cfgrd_nowt Procedure 16.6.9. BFM Configuration Procedures 16.6.10. BFM Shared Memory Access Procedures 16.6.11. BFM Log and Message Procedures 16.6.12. Verilog HDL Formatting Functions
16.6.9. BFM Configuration Procedures x
16.6.9.1. ebfm_cfg_rp_ep Procedure 16.6.9.2. ebfm_cfg_decode_bar Procedure
16.6.10. BFM Shared Memory Access Procedures x
16.6.10.1. Shared Memory Constants 16.6.10.2. shmem_write Task 16.6.10.3. shmem_read Function 16.6.10.4. shmem_display Verilog HDL Function 16.6.10.5. shmem_fill Procedure 16.6.10.6. shmem_chk_ok Function
16.6.11. BFM Log and Message Procedures x
16.6.11.1. ebfm_display Verilog HDL Function 16.6.11.2. ebfm_log_stop_sim Verilog HDL Function 16.6.11.3. ebfm_log_set_suppressed_msg_mask Task 16.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.6.11.5. ebfm_log_open Verilog HDL Function 16.6.11.6. ebfm_log_close Verilog HDL Function
16.6.12. Verilog HDL Formatting Functions x
16.6.12.1. himage1 16.6.12.2. himage2 16.6.12.3. himage4 16.6.12.4. himage8 16.6.12.5. himage16 16.6.12.6. dimage1 16.6.12.7. dimage2 16.6.12.8. dimage3 16.6.12.9. dimage4 16.6.12.10. dimage5 16.6.12.11. dimage6 16.6.12.12. dimage7
16.7. Setting Up Simulation x
16.7.1. Changing Between Serial and PIPE Simulation 16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 16.7.3. Viewing the Important PIPE Interface Signals 16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 16.7.6. Changing between the Hard and Soft Reset Controller
17. Debugging x
17.1. Hardware Bring-Up Issues 17.2. Link Training 17.3. Use Third-Party PCIe Analyzer 17.4. BIOS Enumeration Issues
17.2. Link Training x
17.2.1. Debugging Link that Fails To Reach L0 17.2.2. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History Stratix V Avalon® -ST Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Stratix V Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

3.3.4. Partial Transcript for Configuration Space Bypass Simulation

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

  • Various configuration reads and writes to the Avalon‑MM Stratix V Hard IP for PCI Express in your system after the link is initialized
  • Register writes, reads and compares to both functions
  • Burst memory writes, reads, and compares to both functions

The following example shows the transcript from a successful simulation run.

Transcript from ModelSim Simulation of Gen1 x4 Endpoint


# INFO: 464 ns Completed initial configuration of Root Port. 
# 495000: INFO: top_tb.top_inst_reset_bfm.reset_deassert: Reset deasserted
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE 
# INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE 
# INFO: 17257 ns RP LTSSM State: DETECT.QUIET 
# INFO: 20473 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 21193 ns RP LTSSM State: POLLING.ACTIVE 
# INFO: 29909 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 30949 ns EP LTSSM State: POLLING.ACTIVE	
# INFO: 33957 ns EP LTSSM State: POLLING.CONFIG 
# INFO: 34025 ns RP LTSSM State: DETECT.QUIET 
# INFO: 37241 ns RP LTSSM State: DETECT.ACTIVE 
# INFO: 37961 ns RP LTSSM State: POLLING.ACTIVE 
# INFO: 39945 ns RP LTSSM State: POLLING.CONFIG 
# INFO: 41033 ns RP LTSSM State: CONFIG.LINKWIDTH.START 
# INFO: 41445 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 41765 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 
# INFO: 42057 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 
# INFO: 42249 ns RP LTSSM State: CONFIG.LANENUM.WAIT 
# INFO: 42789 ns EP LTSSM State: CONFIG.LANENUM.WAIT 
# INFO: 43033 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT 
# INFO: 43109 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 43225 ns RP LTSSM State: CONFIG.COMPLETE 
# INFO: 43685 ns EP LTSSM State: CONFIG.COMPLETE 
# INFO: 44953 ns RP LTSSM State:CONFIG.IDLE 
# INFO: 47941 ns EP LTSSM State: CONFIG.IDLE 
# INFO: 48089 ns RP LTSSM State: L0 
# INFO: 48133 ns EP LTSSM State: L0 
# INFO: 48226 ns Configuring Bus 000, Device 000, Function 00 
# INFO: 48226 ns RP Read Only Configuration Registers: 
# INFO: 48226 ns Vendor ID: 1556 
# INFO: 48226 ns Device ID: 5555 
# INFO: 48226 ns Revision ID: 00 
# INFO: 48226 ns Class Code: 040000 
# INFO: 48706 ns ECRC Check Capable: Supported 
# INFO: 48706 ns ECRC Generation Capable: Supported 
# INFO: 48738 ns RP PCI Express Slot Capability 
# INFO: 48738 ns Power Controller: Not Present 
# INFO: 48738 ns MRL Sensor: Not Present 
# INFO: 48738 ns Attention Indicator: Not Present 
# INFO: 48738 ns Power Indicator: Not Present 
# INFO: 48738 ns Hot-Plug Surprise: Not Supported 
# INFO: 48738 ns Hot-Plug Capable: Not Supported 
# INFO: 48738 ns Slot Power Limit Value: 0 
# INFO: 48738 ns Slot Power Limit Scale: 0 
# INFO: 48738 ns Physical Slot Number: 0 
# INFO: 48738 ns Activity_toggle flag is set 
# INFO: 48802 ns RP PCI Express Link Status Register (0081): 
# INFO: 48802 ns RP PCI Express Max Link Speed (0002): 
# INFO: 48802 ns RP PCI Express Current Link Speed (0001):
# INFO: 48802 ns Negotiated Link Width: x8 
# INFO: 48802 ns Slot Clock Config: Local Clock Used 
# INFO: 48834 ns Current Link Speed: 2.5GT/s 
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 49669 ns EP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 50501 ns EP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 51209 ns RP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 53669 ns EP LTSSM State: RECOVERY.SPEED 
# INFO: 54721 ns RP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 54746 ns Wait for Link to enter L0 after negotiated to 
#  the expected speed of EP Target Link Speed 0002): 
# INFO: 53337 ns RP LTSSM State: RECOVERY.SPEED 
# INFO: 55235 ns EP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 56299 ns EP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 57163 ns RP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 57707 ns RP LTSSM State: RECOVERY.IDLE 
# INFO: 57979 ns EP LTSSM State: RECOVERY.IDLE 
# INFO: 58035 ns RP LTSSM State: L0 
# INFO: 58075 ns EP LTSSM State: L0 
# INFO: 58090 ns New Link Speed: 5.0GT/s 
# INFO: 58106 ns RP PCI Express Link Control Register (0000): 
# INFO: 58106 ns Common Clock Config: Local Clock 
# INFO: 70602 ns Completed configuration of Endpoint BARs. 
# INFO: 70602 ns TASK:my_test Setup 
# INFO: 70602 ns TASK:my_test Write to 32bit register at 
#   addr = 0x0 with wdata=0xBABEFACE 
# INFO: 70610 ns TASK:my_test Read from 32bit register at
#    addr 0x00000000 
# INFO: 71298 ns TASK:my_test Register compare matches! 
# INFO: 71298 ns TASK:my_test Write to 32bit register at 
#   0x00000004 Actual 0x12345678 
# INFO: 71306 ns TASK:my_test => 1.22 Read from 32bit register
#   at addr = 0x00000004 
# INFO: 71994 ns TASK:my_test => 1.23 Register compare matches! 
# INFO  71994 ns TASK:my_test => 2.11 Fill write memory with
#   QWORD_INC pattern 
# INFO: 71994 ns TASK:my_test Memory write burst at addr=0x00
#   with wdata=0x10203040 
# INFO: 72002 ns TASK:my_test => 2.21 Memory Read burst 
# INFO: 72690 ns TASK:my_test Memory write burst at addr=0x04
#   with wdata=0x10203040 
# INFO: 72698 ns TASK:my_test Memory Read burst 
# INFO: 73354 ns TASK:my_test Memory write burst at addr=0x08
#   with wdata=0x10203040 
# INFO: 73362 ns TASK:my_test => 2.21 Memory Read burst
# INFO: 74178 ns TASK:my_test Memory write burst at addr=0x0C
#   with wdata=0x10203040 
# INFO: 88154 ns Enumerate EP function = 0x01 
# INFO: 88154 ns cfgbp_enum_config_space Setup config space 
#   for func = 00000001
# INFO: 88154 ns Config Read # INFO:   88946 ns CfgRD at 
#   addr =0x00000000 returns data = 0xE0011172 
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable
#   bit in Command register00000001 
# INFO: 88946 ns Read Modified WRite to config register
#   = 0x00000004 in func = 0x00000001 
# INFO: 115370 ns TASK:my_test; 2.21 Memory Read burst 
# SUCCESS: Simulation stopped due to successful completion! 
# Break in Function ebfm_log_stop_sim at 
#   /..//top_tb/simulation/submodules//altpcietb_bfm_log.v line 78 
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit
#   in Command register00000001 
# INFO: 88946 ns Read Modified WRite to config register = 
#   0x00000004 in func = 0x00000001 
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit
#   in Command register00000001 
# INFO: 88946 ns Read config reg 
# INFO: 89738 ns Original config read data = 00000000 
# INFO: 89738 ns Config write with data = 00000006 
# INFO: 91338 ns After cfg_rd_modified_wr, config_data 
#   = 0x00000006 
# INFO: 92938 ns CfgRD at BAR0 (addr =0x00000010) returns 
#   data = 0xFFF0000C 
# INFO: 94530 ns CfgRD at addr =0x00000010 returns data
#   = 0x8000000C 
# INFO: 97658 ns BAR Address Assignments: 
# INFO: 97658 ns BAR Size Assigned Address Type 
# INFO: 97658 ns BAR1:0 1 MBytes 00000001 00000000 Prefetchable 
# INFO: 97658 ns BAR2 Disabled 
# INFO: 97658 ns BAR3 Disabled
# INFO: 97658 ns BAR4 Disabled 
# INFO: 97658 ns BAR5 Disabled 
# INFO: 97658 ns ExpROM Disabled 
# INFO: 98794 ns Completed configuration of Endpoint BARs. 
# INFO: 98794 ns TASK:my_test Setup 
# INFO: 98794 ns TASK:my_test Write to 32bit register at 0x000000
#   with wdata=0xBABEFACE 
# INFO: 98802 ns TASK:my_test 1.12 Read from 32bit register 
#   at addr = 0x00000000 
# INFO: 9490 ns TASK:my_test 1.13 Register compare matches!
# INFO: 115370 ns TASK:my_test 2.21 Memory Read burst 
# SUCCESS: Simulation stopped due to successful completion! 
# Break in Function ebfm_log_stop_sim at 
#   ./..//top_tb/simulation/submodules//altpcietb_bfm_log.v
# line 78
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