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1. Datasheet
2. Getting Started with the Stratix V Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History
2.1.1. Generating the Testbench
2.1.2. Simulating the Example Design
2.1.3. Generating Synthesis Files
2.1.4. Understanding the Files Generated
2.1.5. Understanding Simulation Log File Generation
2.1.6. Understanding Physical Placement of the PCIe IP Core
2.1.7. Compiling the Design in the Qsys Design Flow
2.1.8. Modifying the Example Design
2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface
3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface
3.3.4. Partial Transcript for Configuration Space Bypass Simulation
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Configuration Space Bypass Mode Interface Signals
5.9. Parity Signals
5.10. LMI Signals
5.11. Transaction Layer Configuration Space Signals
5.12. Hard IP Reconfiguration Interface
5.13. Power Management Signals
5.14. Physical Layer Interface Signals
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. CvP Registers
6.7. Uncorrectable Internal Error Mask Register
6.8. Uncorrectable Internal Error Status Register
6.9. Correctable Internal Error Mask Register
6.10. Correctable Internal Error Status Register
16.6.1. ebfm_barwr Procedure
16.6.2. ebfm_barwr_imm Procedure
16.6.3. ebfm_barrd_wait Procedure
16.6.4. ebfm_barrd_nowt Procedure
16.6.5. ebfm_cfgwr_imm_wait Procedure
16.6.6. ebfm_cfgwr_imm_nowt Procedure
16.6.7. ebfm_cfgrd_wait Procedure
16.6.8. ebfm_cfgrd_nowt Procedure
16.6.9. BFM Configuration Procedures
16.6.10. BFM Shared Memory Access Procedures
16.6.11. BFM Log and Message Procedures
16.6.12. Verilog HDL Formatting Functions
16.7.1. Changing Between Serial and PIPE Simulation
16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
16.7.3. Viewing the Important PIPE Interface Signals
16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
16.7.6. Changing between the Hard and Soft Reset Controller
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1.10. Creating a Design for PCI Express
Select the PCIe variant that best meets your design requirements.
- Is your design an Endpoint or Root Port?
- What Generation do you intend to implement?
- What link width do you intend to implement?
- What bandwidth does your application require?
- Does your design require Configuration via Protocol (CvP)?
Note: The following steps only provide a high-level overview of the design generation and simulation process. For more details, refer to the Quick Start Guide chapter.
- Select parameters for that variant.
- For Intel® Arria® 10 devices, you can use the new Example Design tab of the component GUI to generate a design that you specify. Then, you can simulate this example and also download it to an Intel® Arria® 10 FPGA Development Kit. Refer to the Intel® Arria® 10/ Intel® Cyclone® 10 GX PCI Express* IP Core Quick Start Guide for details.
- For all devices, you can simulate using an Intel-provided example design. All static PCI Express example designs are available under <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>_ed/example_design/<dev> . Alternatively, create a simulation model and use your own custom or third-party BFM. The Platform Designer Generate menu generates simulation models. Intel supports ModelSim* - Intel FPGA Edition for all IP. The PCIe cores support the Aldec RivieraPro*, Cadence NCSim*, Mentor Graphics ModelSim*, and Synopsys VCS* and VCS-MX* simulators.
The Intel testbench and Root Port or Endpoint BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. However, the testbench and Root Port BFM are not intended to be a substitute for a full verification environment. To thoroughly test your application, Intel suggests that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing, or both.
- Compile your design using the Quartus® Prime software. If the versions of your design and the Quartus® Prime software you are running do not match, regenerate your PCIe design.
- Download your design to an Intel development board or your own PCB. Click on the All Development Kits link below for a list of Intel's development boards.
- Test the hardware. You can use Intel's Signal Tap Logic Analyzer or a third-party protocol analyzer to observe behavior.
- Substitute your Application Layer logic for the Application Layer logic in Intel's testbench. Then repeat Steps 3–6. In Intel's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.