Avalon® Interface Specifications

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ID 683091
Date 1/24/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
1. Introduction to the Avalon® Interface Specifications x
1.1. Avalon® Properties and Parameters 1.2. Signal Roles 1.3. Interface Timing 1.4. Example: Avalon® Interfaces in System Designs
2. Avalon® Clock and Reset Interfaces x
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
3. Avalon® Memory-Mapped Interfaces x
3.1. Introduction to Avalon® Memory-Mapped Interfaces 3.2. Avalon® Memory Mapped Interface Signal Roles 3.3. Interface Properties 3.4. Timing 3.5. Transfers 3.6. Address Alignment 3.7. Avalon® -MM Agent Addressing
3.5. Transfers x
3.5.1. Typical Read and Write Transfers 3.5.2. Transfers Using the waitrequestAllowance Property 3.5.3. Read and Write Transfers with Fixed Wait-States 3.5.4. Pipelined Transfers 3.5.5. Burst Transfers 3.5.6. Read and Write Responses
3.5.2. Transfers Using the waitrequestAllowance Property x
3.5.2.1. waitrequestAllowance Equals Two 3.5.2.2. waitrequestAllowance Equals One 3.5.2.3. waitrequestAllowance Equals Two - Not Recommended 3.5.2.4. waitrequestAllowance Compatibility for Avalon® -MM Host and Agent Interfaces 3.5.2.5. waitrequestAllowance Error Conditions
3.5.4. Pipelined Transfers x
3.5.4.1. Pipelined Read Transfer with Variable Latency 3.5.4.2. Pipelined Read Transfers with Fixed Latency
3.5.5. Burst Transfers x
3.5.5.1. Write Bursts 3.5.5.2. Read Bursts 3.5.5.3. Line–Wrapped Bursts
3.5.6. Read and Write Responses x
3.5.6.1. Transaction Order for Avalon® -MM Read and Write Responses (Hosts and Agents) 3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram
3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram x
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
4. Avalon® Interrupt Interfaces x
4.1. Interrupt Sender 4.2. Interrupt Receiver
4.1. Interrupt Sender x
4.1.1. Avalon® Interrupt Sender Signal Roles 4.1.2. Interrupt Sender Properties
4.2. Interrupt Receiver x
4.2.1. Avalon® Interrupt Receiver Signal Roles 4.2.2. Interrupt Receiver Properties 4.2.3. Interrupt Timing
5. Avalon® Streaming Interfaces x
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.3. Signal Sequencing and Timing x
5.3.1. Synchronous Interface 5.3.2. Clock Enables
5.9. Data Transfer with Backpressure x
5.9.1. Data Transfers Using readyLatency and readyAllowance 5.9.2. Data Transfers Using readyLatency
6. Avalon® Streaming Credit Interfaces x
6.1. Terms and Concepts 6.2. Avalon® Streaming Credit Interface Signal Roles 6.3. Avalon® Streaming Credit User Signals
6.2. Avalon® Streaming Credit Interface Signal Roles x
6.2.1. Synchronous Interface 6.2.2. Typical Data Transfers 6.2.3. Returning the Credits
6.3. Avalon® Streaming Credit User Signals x
6.3.1. Per-Symbol User Signal 6.3.2. Per-Packet User Signal
7. Avalon® Conduit Interfaces x
7.1. Avalon® Conduit Signal Roles 7.2. Conduit Properties
8. Avalon® Tristate Conduit Interface x
8.1. Avalon® Tristate Conduit Signal Roles 8.2. Tristate Conduit Properties 8.3. Tristate Conduit Timing
1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications

3.7. Avalon® -MM Agent Addressing

Dynamic bus sizing manages data during transfers between host-agent pairs of differing data widths. Agent data are aligned in contiguous bytes in the host address space.

If the host data width is wider than the agent data width, words in the host address space map to multiple locations in the agent address space. For example, a 32-bit host read from a 16-bit agent results in two read transfers on the agent side. The reads are to consecutive addresses.

If the host is narrower than the agent, then the interconnect manages the agent byte lanes. During host read transfers, the interconnect presents only the appropriate byte lanes of agent data to the narrower host. During host write transfers, the interconnect automatically asserts the byteenable signals to write data only to the specified agent byte lanes.

Agents must have a data width of 8, 16, 32, 64, 128, 256, 512 or 1024 bits. The following table shows the alignment for agent data of various widths within a 32-bit host performing full-word accesses. In this table, OFFSET[N] refers to a agent word size offset into the agent address space.

Table 12.  Dynamic Bus Sizing Host-to-Agent Address Mapping
Host Byte Address  (1) Access 32-Bit Host Data
When Accessing 
an 8-Bit Agent Interface When Accessing 
a 16-Bit Agent Interface When Accessing 
a 64-Bit Agent Interface
0x00 1 OFFSET[0] 7..0 OFFSET[0] 15..0  (2) OFFSET[0] 31..0
2 OFFSET[1] 7..0 OFFSET[1] 15..0 —
3 OFFSET[2] 7..0 — —
4 OFFSET[3] 7..0 — —
0x04 1 OFFSET[4] 7..0 OFFSET[2] 15..0 OFFSET[0] 63..32
2 OFFSET[5] 7..0 OFFSET[3] 15..0 —
3 OFFSET[6] 7..0 — —
4 OFFSET[7] 7..0 — —
0x08 1 OFFSET[8] 7..0 OFFSET[4] 15..0 OFFSET[1] 31..0
2 OFFSET[9] 7..0 OFFSET[5] 15..0 —
3 OFFSET[10] 7..0 — —
4 OFFSET[11] 7..0 — —
0x0C 1 OFFSET[12] 7..0 OFFSET[6] 15..0 OFFSET[1] 63..32
2 OFFSET[13] 7..0 OFFSET[7] 15..0 —
3 OFFSET[14] 7..0 — —
4 OFFSET[15] 7..0 — —
And so on   And so on And so on And so on
Notes:
  1. Although the host issues byte addresses, the host accesses full 32-bit words.
  2. For all agent entries, [<n>] is the word offset and the subscript values are the bits in the word.
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