Avalon® Interface Specifications

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ID 683091
Date 1/24/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
1. Introduction to the Avalon® Interface Specifications x
1.1. Avalon® Properties and Parameters 1.2. Signal Roles 1.3. Interface Timing 1.4. Example: Avalon® Interfaces in System Designs
2. Avalon® Clock and Reset Interfaces x
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
3. Avalon® Memory-Mapped Interfaces x
3.1. Introduction to Avalon® Memory-Mapped Interfaces 3.2. Avalon® Memory Mapped Interface Signal Roles 3.3. Interface Properties 3.4. Timing 3.5. Transfers 3.6. Address Alignment 3.7. Avalon® -MM Agent Addressing
3.5. Transfers x
3.5.1. Typical Read and Write Transfers 3.5.2. Transfers Using the waitrequestAllowance Property 3.5.3. Read and Write Transfers with Fixed Wait-States 3.5.4. Pipelined Transfers 3.5.5. Burst Transfers 3.5.6. Read and Write Responses
3.5.2. Transfers Using the waitrequestAllowance Property x
3.5.2.1. waitrequestAllowance Equals Two 3.5.2.2. waitrequestAllowance Equals One 3.5.2.3. waitrequestAllowance Equals Two - Not Recommended 3.5.2.4. waitrequestAllowance Compatibility for Avalon® -MM Host and Agent Interfaces 3.5.2.5. waitrequestAllowance Error Conditions
3.5.4. Pipelined Transfers x
3.5.4.1. Pipelined Read Transfer with Variable Latency 3.5.4.2. Pipelined Read Transfers with Fixed Latency
3.5.5. Burst Transfers x
3.5.5.1. Write Bursts 3.5.5.2. Read Bursts 3.5.5.3. Line–Wrapped Bursts
3.5.6. Read and Write Responses x
3.5.6.1. Transaction Order for Avalon® -MM Read and Write Responses (Hosts and Agents) 3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram
3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram x
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
4. Avalon® Interrupt Interfaces x
4.1. Interrupt Sender 4.2. Interrupt Receiver
4.1. Interrupt Sender x
4.1.1. Avalon® Interrupt Sender Signal Roles 4.1.2. Interrupt Sender Properties
4.2. Interrupt Receiver x
4.2.1. Avalon® Interrupt Receiver Signal Roles 4.2.2. Interrupt Receiver Properties 4.2.3. Interrupt Timing
5. Avalon® Streaming Interfaces x
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.3. Signal Sequencing and Timing x
5.3.1. Synchronous Interface 5.3.2. Clock Enables
5.9. Data Transfer with Backpressure x
5.9.1. Data Transfers Using readyLatency and readyAllowance 5.9.2. Data Transfers Using readyLatency
6. Avalon® Streaming Credit Interfaces x
6.1. Terms and Concepts 6.2. Avalon® Streaming Credit Interface Signal Roles 6.3. Avalon® Streaming Credit User Signals
6.2. Avalon® Streaming Credit Interface Signal Roles x
6.2.1. Synchronous Interface 6.2.2. Typical Data Transfers 6.2.3. Returning the Credits
6.3. Avalon® Streaming Credit User Signals x
6.3.1. Per-Symbol User Signal 6.3.2. Per-Packet User Signal
7. Avalon® Conduit Interfaces x
7.1. Avalon® Conduit Signal Roles 7.2. Conduit Properties
8. Avalon® Tristate Conduit Interface x
8.1. Avalon® Tristate Conduit Signal Roles 8.2. Tristate Conduit Properties 8.3. Tristate Conduit Timing
1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications

3.3. Interface Properties

Table 10.   Avalon® -MM Interface Properties
Name Default Value Legal Values Description
addressUnits Host - symbols

Agent -words

 words, symbols

Specifies the unit for addresses. A symbol is typically a byte.

Refer to the definition of address in the Avalon® Memory-Mapped Interface Signal Types table for the typical use of this property.

alwaysBurstMaxBurst false true, false When true, indicates that the host always issues the maximum-length burst. The maximum burst length is 2 burstcount_width - 1 . This parameter has no effect for Avalon® -MM agent interfaces.
burstcountUnits words words, symbols This property specifies the units for the burstcount signal. For symbols, the burstcount value is interpreted as the number of symbols (bytes) in the burst. For words, the burstcount value is interpreted as the number of word transfers in the burst.
burstOnBurstBoundariesOnly false true, false If true, burst transfers presented to this interface begin at addresses which are multiples of the maximum burst size.
constantBurstBehavior Host -false

Agent -false

true, false Hosts: When true, declares that the host holds address and burstcount constant throughout a burst transaction. When false (default), declares that the host holds address and burstcount constant only for the first beat of a burst.

Agents: When true, declares that the agent expects address and burstcount to be held constant throughout a burst. When false (default), declares that the agent samples address and burstcount only on the first beat of a burst.

holdTime(1) 0 0 – 1000 cycles Specifies time in timingUnits between the deassertion of write and the deassertion of address and data. (Only applies to write transactions.)
linewrapBursts false true, false Some memory devices implement a wrapping burst instead of an incrementing burst. When a wrapping burst reaches a burst boundary, the address wraps back to the previous burst boundary. Only the low-order bits are required for address counting. For example, a wrapping burst to address 0xC with burst boundaries every 32 bytes across a 32-bit interface writes to the following addresses:
  • 0xC
  • 0x10
  • 0x14
  • 0x18
  • 0x1C
  • 0x0
  • 0x4
  • 0x8
maximumPendingReadTransactions (1) 1(2) 1 – 64

Agents: This parameter is the maximum number of pending reads that the agent can queue. The value must be non-zero for any agent with the readdatavalid signal.

Refer to Pipelined Read Transfer with Variable Latency for a timing diagram that illustrates this property and for additional information about using waitrequest and readdatavalid with multiple outstanding reads.

Hosts: This property is the maximum number of outstanding read transactions that the host can generate.
Note: Do not set this parameter to 0. (For backwards compatibility, the software supports a parameter setting of 0. However, you should not use this setting in new designs).
maximumPendingWriteTransactions 0 1 – 64

The maximum number of pending non-posted writes that a agent can accept or a host can issue. A agent asserts waitrequest once the interconnect reaches this limit, and the host stops issuing commands.

The default value is 0, which allows unlimited pending write transactions for a host that supports write responses. A agent that supports write responses must set this to a non-zero value.
minimumResponseLatency 1   For interfaces that support readdatavalid or writeresponsevalid, specifies the minimum number of cycles between a read or write command and the response to the command.
readLatency(1) 0 0 – 63 Read latency for fixed-latency Avalon® -MM agents. For a timing diagram that uses a fixed latency read, refer to Pipelined Read Transfers with Fixed Latency.

Avalon® -MM agents that are fixed latency must provide a value for this interface property. Avalon® -MM agents that are variable latency use the readdatavalid signal to specify valid data.

readWaitTime(1) 1 0 – 1000 cycles For interfaces that do not use the waitrequest signal. readWaitTime indicates the timing in timingUnits before the agents accepts a read command. The timing is as if the agent asserted waitrequest for readWaitTime cycles.
setupTime(1) 0 0 – 1000 cycles Specifies time in timingUnits between the assertion of address and data and assertion of read or write.
timingUnits(1) cycles

cycles,

nanoseconds

 Specifies the units for setupTime, holdTime, writeWaitTime and readWaitTime. Use cycles for synchronous devices and nanoseconds for asynchronous devices. Almost all Avalon® -MM agent devices are synchronous.

An Avalon® -MM component that bridges from an Avalon® -MM agent interface to an off-chip device may be asynchronous. That off-chip device might have a fixed settling time for bus turnaround.

waitrequestAllowance 0  

Specifies the number of transfers that can be issued or accepted after waitrequest is asserted.

When the waitrequestAllowance is 0, the write, read and waitrequest signals maintain their existing behavior as described in the Avalon® -MM Signal Roles table.

When the waitrequestAllowance is greater than 0, every clock cycle on which write or read is asserted counts as a command transfer. Once waitrequest is asserted, only waitrequestAllowance more command transfers are legal while waitrequest remains asserted. After the waitrequestAllowance is reached, write and read must remain deasserted for as long as waitrequest is asserted.

Once waitrequestdeasserts, transfers may resume at any time without restrictions until waitrequest asserts again. At this time, waitrequestAllowance more transfers may complete while waitrequest remains asserted.

writeWaitTime(1) 0 0 – 1000 Cycles For interfaces that do not use the waitrequest signal, writeWaitTime specifies the timing in timingUnits before a agent accepts a write. The timing is as if the agent asserted waitrequest for writeWaitTime cycles or nanoseconds.

For a timing diagram that illustrates the use of writeWaitTime, refer to Read and Write Transfers with Fixed Wait-States.

Interface Relationship Properties
associatedClock N/A N/A Name of the clock interface to which this Avalon® -MM interface is synchronous.
associatedReset N/A N/A Name of the reset interface which resets the logic on this Avalon® -MM interface.
bridgesToHost 0 Avalon® -MM Host name on the same component An Avalon® -MM bridge consists of a agent and a host, and has the property that an access to the agent requesting a byte or bytes causes the same byte or bytes to be requested by the host. The Avalon® -MM Pipeline Bridge in the Platform Designer component library implements this functionality.
Notes:
  1. Although this property characterizes a agent device, hosts can declare this property to enable direct connections between matching host and agent interfaces.
  2. If a agent interface accepts more read transfers than allowed, the interconnect pending read FIFO may overflow with unpredictable results. The agent may lose readdata or route readdata to the wrong host interface. Or, the system may lock up. The agent interface must assert waitrequest to prevent this overflow.
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