Avalon® Interface Specifications

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ID 683091
Date 1/24/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
1. Introduction to the Avalon® Interface Specifications x
1.1. Avalon® Properties and Parameters 1.2. Signal Roles 1.3. Interface Timing 1.4. Example: Avalon® Interfaces in System Designs
2. Avalon® Clock and Reset Interfaces x
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
3. Avalon® Memory-Mapped Interfaces x
3.1. Introduction to Avalon® Memory-Mapped Interfaces 3.2. Avalon® Memory Mapped Interface Signal Roles 3.3. Interface Properties 3.4. Timing 3.5. Transfers 3.6. Address Alignment 3.7. Avalon® -MM Agent Addressing
3.5. Transfers x
3.5.1. Typical Read and Write Transfers 3.5.2. Transfers Using the waitrequestAllowance Property 3.5.3. Read and Write Transfers with Fixed Wait-States 3.5.4. Pipelined Transfers 3.5.5. Burst Transfers 3.5.6. Read and Write Responses
3.5.2. Transfers Using the waitrequestAllowance Property x
3.5.2.1. waitrequestAllowance Equals Two 3.5.2.2. waitrequestAllowance Equals One 3.5.2.3. waitrequestAllowance Equals Two - Not Recommended 3.5.2.4. waitrequestAllowance Compatibility for Avalon® -MM Host and Agent Interfaces 3.5.2.5. waitrequestAllowance Error Conditions
3.5.4. Pipelined Transfers x
3.5.4.1. Pipelined Read Transfer with Variable Latency 3.5.4.2. Pipelined Read Transfers with Fixed Latency
3.5.5. Burst Transfers x
3.5.5.1. Write Bursts 3.5.5.2. Read Bursts 3.5.5.3. Line–Wrapped Bursts
3.5.6. Read and Write Responses x
3.5.6.1. Transaction Order for Avalon® -MM Read and Write Responses (Hosts and Agents) 3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram
3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram x
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
4. Avalon® Interrupt Interfaces x
4.1. Interrupt Sender 4.2. Interrupt Receiver
4.1. Interrupt Sender x
4.1.1. Avalon® Interrupt Sender Signal Roles 4.1.2. Interrupt Sender Properties
4.2. Interrupt Receiver x
4.2.1. Avalon® Interrupt Receiver Signal Roles 4.2.2. Interrupt Receiver Properties 4.2.3. Interrupt Timing
5. Avalon® Streaming Interfaces x
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.3. Signal Sequencing and Timing x
5.3.1. Synchronous Interface 5.3.2. Clock Enables
5.9. Data Transfer with Backpressure x
5.9.1. Data Transfers Using readyLatency and readyAllowance 5.9.2. Data Transfers Using readyLatency
6. Avalon® Streaming Credit Interfaces x
6.1. Terms and Concepts 6.2. Avalon® Streaming Credit Interface Signal Roles 6.3. Avalon® Streaming Credit User Signals
6.2. Avalon® Streaming Credit Interface Signal Roles x
6.2.1. Synchronous Interface 6.2.2. Typical Data Transfers 6.2.3. Returning the Credits
6.3. Avalon® Streaming Credit User Signals x
6.3.1. Per-Symbol User Signal 6.3.2. Per-Packet User Signal
7. Avalon® Conduit Interfaces x
7.1. Avalon® Conduit Signal Roles 7.2. Conduit Properties
8. Avalon® Tristate Conduit Interface x
8.1. Avalon® Tristate Conduit Signal Roles 8.2. Tristate Conduit Properties 8.3. Tristate Conduit Timing
1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications

5.9. Data Transfer with Backpressure

The sink asserts ready for a single clock cycle to indicate it is ready for an active cycle. If the sink is ready for data, the cycle is a ready cycle. During a ready cycle, the source may assert valid and provide data to the sink. If the source has no data to send, the source deasserts valid and can drive data to any value.

Interfaces that support backpressure define the readyLatency parameter to indicate the number of cycles from the time that ready is asserted until valid data can be driven. If the readyLatency is nonzero, cycle <n + readyLatency> is a ready cycle if ready is asserted on cycle <n>.

When readyLatency = 0, data transfer only happens when ready and valid are asserted on the same cycle. In this mode, the source does not receive the sink’s ready signal before sending valid data. The source provides the data and asserts valid whenever the source has valid data. The source waits for the sink to capture the data and assert ready. The source can change the data at any time. The sink only captures input data from the source when ready and valid are both asserted.

When readyLatency >= 1, the sink asserts ready before the ready cycle itself. The source can respond during the appropriate subsequent cycle by asserting valid. The source may not assert valid during cycles that are not ready cycles.

readyAllowance defines the number of transfers that the sink can capture when ready is deasserted. When readyAllowance = 0, the sink cannot accept any transfers after ready is deasserted. If readyAllowance = <n> where n > 0, the sink can accept up to <n> transfers after ready is deasserted.

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