Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

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ID 683082
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Recommended HDL Coding Styles 2. Recommended Design Practices 3. Managing Metastability with the Intel® Quartus® Prime Software 4. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Recommended HDL Coding Styles x
1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
1.1. Using Provided HDL Templates x
1.1.1. Inserting HDL Code from a Provided Template
1.3. Inferring Multipliers and DSP Functions x
1.3.1. Inferring Multipliers 1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions
1.4. Inferring Memory Functions from HDL Code x
1.4.1. Inferring RAM functions from HDL Code 1.4.2. Inferring ROM Functions from HDL Code 1.4.3. Inferring Shift Registers in HDL Code 1.4.4. Inferring FIFOs in HDL Code
1.4.1. Inferring RAM functions from HDL Code x
1.4.1.1. Use Synchronous Memory Blocks 1.4.1.2. Avoid Unsupported Reset and Control Conditions 1.4.1.3. Check Read-During-Write Behavior 1.4.1.4. Controlling RAM Inference and Implementation 1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM 1.4.1.8. True Dual-Port Synchronous RAM 1.4.1.9. Mixed-Width Dual-Port RAM 1.4.1.10. RAM with Byte-Enable Signals 1.4.1.11. Specifying Initial Memory Contents at Power-Up
1.4.3. Inferring Shift Registers in HDL Code x
1.4.3.1. Simple Shift Register 1.4.3.2. Shift Register with Evenly Spaced Taps
1.4.4. Inferring FIFOs in HDL Code x
1.4.4.1. Dual Clock FIFO Example in Verilog HDL 1.4.4.2. Dual Clock FIFO Timing Constraints
1.5. Register and Latch Coding Guidelines x
1.5.1. Register Power-Up Values 1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable 1.5.3. Latches
1.5.1. Register Power-Up Values x
1.5.1.1. Specifying a Power-Up Value
1.5.3. Latches x
1.5.3.1. Avoid Unintentional Latch Generation 1.5.3.2. Inferring Latches Correctly
1.6. General Coding Guidelines x
1.6.1. Tri-State Signals 1.6.2. Clock Multiplexing 1.6.3. Adder Trees 1.6.4. State Machine HDL Guidelines 1.6.5. Multiplexer HDL Guidelines 1.6.6. Cyclic Redundancy Check Functions 1.6.7. Comparator HDL Guidelines 1.6.8. Counter HDL Guidelines
1.6.3. Adder Trees x
1.6.3.1. Architectures with 6-Input LUTs in Adaptive Logic Modules
1.6.4. State Machine HDL Guidelines x
1.6.4.1. State Machine Power-Up 1.6.4.2. Verilog HDL State Machines 1.6.4.3. VHDL State Machines
1.6.4.2. Verilog HDL State Machines x
1.6.4.2.1. Verilog-2001 State Machine Coding Example 1.6.4.2.2. SystemVerilog State Machine Coding Example
1.6.4.3. VHDL State Machines x
1.6.4.3.1. VHDL State Machine Coding Example
1.6.5. Multiplexer HDL Guidelines x
1.6.5.1. Intel® Quartus® Prime Software Option for Multiplexer Restructuring 1.6.5.2. Multiplexer Types 1.6.5.3. Implicit Defaults in IF Statements 1.6.5.4. default or OTHERS CASE Assignment
1.6.5.2. Multiplexer Types x
1.6.5.2.1. Binary Multiplexers 1.6.5.2.2. Selector Multiplexers 1.6.5.2.3. Priority Multiplexers
1.6.6. Cyclic Redundancy Check Functions x
1.6.6.1. If Performance is Important, Optimize for Speed 1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages 1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 1.6.6.4. Take Advantage of Latency if Available 1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use 1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
2. Recommended Design Practices x
2.1. Following Synchronous FPGA Design Practices 2.2. HDL Design Guidelines 2.3. Use Clock and Register-Control Architectural Features 2.4. Implementing Embedded RAM 2.5. Design Assistant Design Rule Checking 2.6. Recommended Design Practices Revision History
2.1. Following Synchronous FPGA Design Practices x
2.1.1. Implementing Synchronous Designs 2.1.2. Asynchronous Design Hazards
2.2. HDL Design Guidelines x
2.2.1. Considerations for the Intel® Hyperflex™ FPGA Architecture 2.2.2. Optimizing Combinational Logic 2.2.3. Optimizing Clocking Schemes 2.2.4. Optimizing Physical Implementation and Timing Closure 2.2.5. Optimizing Power Consumption 2.2.6. Managing Design Metastability
2.2.2. Optimizing Combinational Logic x
2.2.2.1. Avoid Combinational Loops 2.2.2.2. Avoid Unintended Latch Inference 2.2.2.3. Avoid Delay Chains in Clock Paths 2.2.2.4. Use Synchronous Pulse Generators
2.2.3. Optimizing Clocking Schemes x
2.2.3.1. Register Combinational Logic Outputs 2.2.3.2. Avoid Asynchronous Clock Division 2.2.3.3. Avoid Ripple Counters 2.2.3.4. Use Multiplexed Clocks 2.2.3.5. Use Gated Clocks 2.2.3.6. Use Synchronous Clock Enables
2.2.3.5. Use Gated Clocks x
2.2.3.5.1. Recommended Clock-Gating Methods
2.2.4. Optimizing Physical Implementation and Timing Closure x
2.2.4.1. Planning Physical Implementation 2.2.4.2. Planning FPGA Resources 2.2.4.3. Optimizing for Timing Closure 2.2.4.4. Optimizing Critical Timing Paths
2.3. Use Clock and Register-Control Architectural Features x
2.3.1. Use Global Reset Resources 2.3.2. Use Global Clock Network Resources 2.3.3. Use Clock Region Assignments to Optimize Clock Constraints 2.3.4. Avoid Asynchronous Register Control Signals
2.3.1. Use Global Reset Resources x
2.3.1.1. Use Synchronous Resets 2.3.1.2. Using Asynchronous Resets 2.3.1.3. Use Synchronized Asynchronous Reset
2.3.3. Use Clock Region Assignments to Optimize Clock Constraints x
2.3.3.1. Clock Region Assignments in Intel® Stratix® 10 Devices 2.3.3.2. Clock Region Assignments in Intel® Arria® 10 and Older Device Families
2.5. Design Assistant Design Rule Checking x
2.5.1. Setting Up Design Assistant 2.5.2. Running Design Assistant During Compilation 2.5.3. Running Design Assistant in Analysis Mode 2.5.4. Cross-Probing from Design Assistant 2.5.5. Managing Design Assistant Rules 2.5.6. Design Assistant Rule Categories
2.5.1. Setting Up Design Assistant x
2.5.1.1. Design Assistant Rule Severity Levels
2.5.2. Running Design Assistant During Compilation x
2.5.2.1. Opening Design Assistant Rule Help
2.5.3. Running Design Assistant in Analysis Mode x
2.5.3.1. Launching Design Assistant from Chip Planner 2.5.3.2. Launching Design Assistant from Timing Analyzer
2.5.4. Cross-Probing from Design Assistant x
2.5.4.1. Cross-Probing from Design Assistant to Timing Analyzer 2.5.4.2. Cross-Probing from Design Assistant to Visualization Tools
2.5.5. Managing Design Assistant Rules x
2.5.5.1. Changing the Default Number of Violations per Rule 2.5.5.2. Enabling Rules for Specific Compiler Stages 2.5.5.3. Specifying Rule Parameters for a Specific Compiler Stage 2.5.5.4. Modifying Rule Severity Levels 2.5.5.5. Waiving Design Assistant Rules 2.5.5.6. Design Assistant Tags
2.5.5.5. Waiving Design Assistant Rules x
2.5.5.5.1. Creating Design Assistant Waivers 2.5.5.5.2. Design Assistant Waiver Dialog Box 2.5.5.5.3. Deleting Design Assistant Waivers 2.5.5.5.4. Design Assistant Waiver Tcl Commands 2.5.5.5.5. drc::add_waiver Command 2.5.5.5.6. drc::get_waivers Command 2.5.5.5.7. drc::report_waivers Command
3. Managing Metastability with the Intel® Quartus® Prime Software x
3.1. Metastability Analysis in the Intel® Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History
3.1. Metastability Analysis in the Intel® Quartus® Prime Software x
3.1.1. Data Synchronization Register Chains 3.1.2. Identify Synchronizers for Metastability Analysis 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
3.2. Metastability and MTBF Reporting x
3.2.1. Metastability Reports 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation
3.2.1. Metastability Reports x
3.2.1.1. MTBF Summary Report 3.2.1.2. Synchronizer Summary Report 3.2.1.3. Synchronizer Chain Statistics Report in the Timing Analyzer
3.2.1.1. MTBF Summary Report x
3.2.1.1.1. Typical and Worst-Case MTBF of Design 3.2.1.1.2. Synchronizer Chains 3.2.1.1.3. Increasing Available Settling Time
3.3. MTBF Optimization x
3.3.1. Synchronization Register Chain Length
3.4. Reducing Metastability Effects x
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
3.5. Scripting Support x
3.5.1. Identifying Synchronizers for Metastability Analysis 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation 3.5.3. report_metastability and Tcl Command 3.5.4. MTBF Optimization 3.5.5. Synchronization Register Chain Length
1. Recommended HDL Coding Styles
2. Recommended Design Practices
3. Managing Metastability with the Intel® Quartus® Prime Software
4. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.6. Recommended Design Practices Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2022.06.20 22.2
  • Removed obsolete Block Based Design rule category from Design Assistant Design Rule Checking topic.
2021.10.04 21.3
  • Updated Design Assistant Design Rule Checking topic for latest rule categories.
2021.03.29 21.1
  • Updated Design Assistant Design Rule Checking topic with screenshot, minor wording changes, and link to AN 919: Improving Quality of Results with Design Assistant.
  • Updated Setting Up Design Assistant topic for rule tags.
  • Updated Running Design Assistant During Compilation step 4 wording.
  • Updated Opening Design Assistant Rule Help topic to show rule included in this release.
  • Updated screenshots in Cross-Probing from Design Assistant to Timing Analyzer topic.
  • Removed Filtering and Hiding Rule Violations section as waivers are most effective method in current version.
  • Updated Changing the Default Number of Violations per Rule for minor wording changes.
  • Created new Design Assistant Tags topic to define all tags.
  • Created new Design Assistant Waiver Dialog Box topic to define all settings in this dialog box. including new waiver features.
  • Updated Creating Design Assistant Waivers topic for waiver preview and reporting.
  • Updated Deleting Design Assistant Waivers topic for new GUI method.
  • Updated Design Assistant Rule Categories topic for latest rule categories.
  • Revised Design Assistant Rule Severity Levels descriptions.
2020.09.28 20.3
  • Added new "Waiving Design Assistant Rules" section.
  • Added new "Cross-Probing with Design Assistant" section.
  • Added description of new Fatal severity level Design Assistant rule to "Modifying Rule Severity Levels" topic.
  • Updated "Setting Up Design Assistant" for new Fatal severity level and RDC rule category.
  • Updated "Running Design Assistant in Analysis Mode" with screenshots and detailed steps.
  • Added RDC to "Design Assistant Rule Categories" topic.
  • Removed individual Design Assistant rule descriptions from document and linked to updated rule description in Help.
  • Replaced obsolete rule screenshots throughout.
2020.04.13 20.1
  • Added support for Design Assistant during Timing Signoff to "Setting Up Design Assistant" and "Running Design Assistant During Compilation" topics.
  • Added new Design Assistant rules.
  • Revised Design Assistant rules HRR-10201, HRR-10201, and RES-30131.
  • Removed various obsolete Design Assistant rules.
2019.11.01 19.3.0
  • Revised "Changing Design Assistant Rule Scope or Number of Violations" topic for clarity.
  • Created separate "Clock Domain Crossing (CDC) Rules" category and topic.
  • Added "CLK-30026: Missing Clock Assignment" Design Assistant rule.
  • Added "CLK-30027: Multiple Clock Assignment" Design Assistant rule.
  • Added "CLK-30028: Invalid Generated Clock" Design Assistant rule.
  • Added "CLK-30029: Invalid Clock Assignment" Design Assistant rule.
  • Added "CLK-30030: PLL Setting Violation" Design Assistant rule.
  • Added "CLK-30031: Input Delay Assigned to Clock" Design Assistant rule.
2019.09.30 19.3.0
  • Added new "Setting Up Design Assistant" topic.
  • Added new "Managing Design Assistant Rules" topic.
  • Added new "Enabling Rules for Specific Compiler Stages" topic.
  • Added new "Specifying Rule Parameters for Specific Compiler Stages" topic.
  • Added new "Modifying Rule Severity Levels" topic.
  • Added new "Filtering and Hiding Rule Violations" topic.
  • Added new "Filter Options Dialog Box" topic.
  • Added new "Linking to Design Assistant Rule Documentation" topic.
  • Updated screenshots for latest GUI elements.
  • Added the following new Design Assistant rules:
    • CDC-50001: Missing 1-Bit Synchronizer
    • CDC-50002: 1-Bit Synchronized Missing Constraint
    • CDC-50003: CE-Type CDC No Constraints
    • HRR-10015: High Fan-out Signal
    • HRR-10201: Registers Cannot Power Up with Don't Care Logic Level
    • HRR-10204: Reset Release Instance Count Check
    • RES-30132: Registers May Not Be Properly Reset
    • TMC-20500: Hierarchical Tree Duplication was Shallower than Possible
    • TMC-20501: Hierarchical Tree Duplication was Shallower than Requested
    • TMC-20550: Duplication Candidate Rejected for Placement Constraint
    • TMC-20551: Automatically-Discovered Duplication Candidate Likely Requires More Duplication
    • TMC-20552: User-Directed Duplication Candidate was Rejected
    • TMC-20601: Registers with High Immediate Fan-Out Tension
    • TMC-20602: Registers with High Timing Path Endpoint Tension
    • TMC-20603: Registers with High Immediate Fan-Out Span
    • TMC-20604: Registers with High Timing Path Endpoint Span
  • Removed obsolete Design Assistant rules:
    • HRR-10014: High Fan-out Nets Driving Clock-Enable Pins
    • HRR-10016: Registers Cannot Power-Up With Dont Care Logic Level
2019.04.01 19.1.0
  • Described new Design Assistant design rule checking tool.
  • Added new topics describing each of the Design Assistant rules, under the Recommended Design Practices > Checking for Design Rule Violations section.
2018.09.24 18.1.0
  • Created subtopics: Clock Region Assignments in Intel Arria 10 and Older Device Families and Clock Region Assignments in Intel Stratix 10 Devices from content in topic: Use Clock Region Assignments to Optimize Clock Constraints.
2017.11.06 17.1.0
  • Updated topic: Optimizing Timing Closure.
  • Updated topic Use Global Clock Network Resources and added topic Use Clock Region Assignments to Optimize Clock Constraints for Intel Stratix 10 support.
2017.05.08 17.0.0
  • Removed information about Integrated Synthesis.
  • Removed information about quartus_drc.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.03 16.0.0
  • Replaced Internally Synchronized Reset code sample with corrected version.
  • Removed information about deprecated physical synthesis options.
  • Removed information about unsupported Design Assistant.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
2014.12.15 14.1.0 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
June 2014 14.0.0 Removed references to obsolete MegaWizard Plug-In Manager.
November 2013 13.1.0 Removed HardCopy device information.
May 2013 13.0.0

Removed PrimeTime support.

June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0 Added information to Reset Resources .
December 2010 10.1.0
  • Title changed from Design Recommendations for Altera Devices and the Quartus II Design Assistant.
  • Updated to new template.
  • Added references to Quartus II Help for “Metastability” on page 9–13 and “Incremental Compilation” on page 9–13.
  • Removed duplicated content and added references to Help for “Custom Rules” on page 9–15.
July 2010 10.0.0
  • Removed duplicated content and added references to Quartus II Help for Design Assistant settings, Design Assistant rules, Enabling and Disabling Design Assistant Rules, and Viewing Design Assistant reports.
  • Removed information from “Combinational Logic Structures” on page 5–4
  • Changed heading from “Design Techniques to Save Power” to “Power Optimization” on page 5–12
  • Added new “Metastability” section
  • Added new “Incremental Compilation” section
  • Added information to “Reset Resources” on page 5–23
  • Removed “Referenced Documents” section
November 2009 9.1.0
  • Removed documentation of obsolete rules.
March 2009 9.0.0
  • No change to content.
November 2008 8.1.0
  • Changed to 8-1/2 x 11 page size
  • Added new section “Custom Rules Coding Examples” on page 5–18
  • Added paragraph to “Recommended Clock-Gating Methods” on page 5–11
  • Added new section: “Design Techniques to Save Power” on page 5–12
May 2008 8.0.0
  • Updated Figure 5–9 on page 5–13; added custom rules file to the flow
  • Added notes to Figure 5–9 on page 5–13
  • Added new section: “Custom Rules Report” on page 5–34
  • Added new section: “Custom Rules” on page 5–34
  • Added new section: “Targeting Embedded RAM Architectural Features” on page 5–38
  • Minor editorial updates throughout the chapter
  • Added hyperlinks to referenced documents throughout the chapter
Level Two Title